HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 107

• Manufacturer Part Number: HD6432160
• Description: Hitachi 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

3.2.3
STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and
selects the input clock of the timer counter.
Bit
7
6
5
4
Bit Name
IICS
IICX1
IICX0
IICE
Serial Timer Control Register (STCR)
Initial Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
I
Specifies bits 7 to 4 of port A as output buffers similar
to SLC and SDA. These pins are used to implement
an I
0: PA7 to PA4 are normal input/output pins.
1: PA7 to PA4 are input/output pins enabling bus
driving.
I
These bits control the IIC operation. These bits select
a transfer rate in master mode together with bits
CKS2 to CKS0 in the I
For details on the transfer rate, refer to table 16.3.
I
Enables or disables CPU access for IIC registers
(ICCR, ICSR, ICDR/SARX, ICMR/SAR), PWMX
registers (DADRAH/DACR, DADRAL,
DADRBH/DACNTH, DADRBL/DACNTL), and SCI
registers (SMR, BRR, SCMR).
0: SCI_1 registers are accessed in an area from
H’(FF)FF88 to H’(FF)FF89 and from H’(FF)FF8E to
H’(FF)FF8F.
SCI_2 registers are accessed in an area from
H’(FF)FFA0 to H’(FF)FFA1 and from H’(FF)FFA6 to
H’(FF)FFA7.
SCI_0 registers are accessed in an area from
H’(FF)FFD8 to H’(FF)FFD9 and from H’(FF)FFDE to
H’(FF)FFDF.
1: IIC_1 registers are accessed in an area from
H’(FF)FF88 to H’(FF)FF89 and from H’(FF)FF8E to
H’(FF)FF8F.
PWMX registers are accessed in an area from
H’(FF)FFA0 to H’(FF)FFA1 and from H’(FF)FFA6 to
H’(FF)FFA7.
IIC_0 registers are accessed in an area from
H’(FF)FFD8 to H’(FF)FFD9 and from H’(FF)FFDE to
H’(FF)FFDF.
2
2
2
C Extra Buffer Select
C Transfer Rate Select 1 and 0
C Master Enable
2
C interface only by software.
Rev. 2.0, 08/02, page 67 of 788
2
C bus mode register (ICMR).