HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 142

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HD6432160

Manufacturer Part Number
HD6432160
Description
Hitachi 16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
3. An interrupt request with interrupt control level 1 is accepted when the I bit is cleared to 0, or
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
6. The I and UI bits in CCR are set to 1. This masks all interrupts except for an NMI or address
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
Rev. 2.0, 08/02, page 102 of 788
when the I bit is set to 1 while the UI bit is cleared to 0.
An interrupt request with interrupt control level 0 is accepted when the I bit is cleared to 0.
When the I bit is set to 1, only an NMI or address break interrupt request is accepted, and other
interrupts are held pending.
When both the I and UI bits are set to 1, only an NMI or address break interrupt request is
accepted, and other interrupts are held pending.
When the I bit is cleared to 0, the UI bit is not affected.
execution of the current instruction has been completed.
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
break interrupt.
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.

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