HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 469
![no-image](/images/no-image-200.jpg)
HD6432160
Manufacturer Part Number
HD6432160
Description
Hitachi 16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6432160.pdf
(829 pages)
- Current page: 469 of 829
- Download datasheet (5Mb)
User processing
(master output)
(master output)
(slave output)
(master output)
(slave output)
(master output)
User processing
Figure 16.9 Example of Operation Timing in Master Transmit Mode (MLS = WAIT = 0)
Note:* Data write
ICDRE
SDA
ICDRE
IRTR
ICDR
Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high,
and generates the stop condition.
ICDRT
ICDRS
SDA
IRIC
SDA
SCL
IRTR
IRIC
SDA
SCL
in ICDR
prohibited
Start condition generation
Data 1
Bit 0
Figure 16.10 Example of Stop Condition Issuance Operation Timing
[4] BBSY set to 1
8
Data 1
[9] ICDR write
SCP cleared to 0
(start condition issuance)
[7]
[5]
A
Interrupt
request
9
in Master Transmit Mode (MLS = WAIT = 0)
Address + R/
Address + R/
Bit 7
Bit 7
[6] ICDR write
1
1
Bit 6
Bit 6
[9] IRIC clear
2
2
Bit 5
Bit 5
Slave address
3
3
Bit 4
Bit 4
[6] IRIC clear
4
4
Data 2
Bit 3
Bit 3
5
5
Bit 2
Bit 2
6
6
Data 2
Bit 1
Bit 1
7
[9] ICDR write
7
[11] ACKB read
R/W
Bit 0
Bit 0
8
Rev. 2.0, 08/02, page 429 of 788
8
[7]
A
9
Interrupt
request
[12] IRIC clear
[10]
A
9
[9] IRIC clear
Start condition issuance
Data 1
[12] Set BBSY=1and
Bit 7
Data 1
1
Data 1
(Stop condition issuance)
SCP=0
Bit 6
2
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