HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 390
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HD6432160
Manufacturer Part Number
HD6432160
Description
Hitachi 16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6432160.pdf
(829 pages)
- Current page: 390 of 829
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15.3.9
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 15.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and
clocked synchronous mode. The initial value of BRR is H'FF, and it can be read from or written to
by the CPU at all times.
Table 15.2 Relationships between N Setting in BRR and Bit Rate B
Mode
Asynchronous mode
Clocked synchronous mode
Legend
B:
N:
ø:
n:
Table 15.3 shows sample N settings in BRR in normal asynchronous mode. Table 15.4 shows the
maximum bit rate settable for each frequency. Table 15.6 shows sample N settings in BRR in
clocked synchronous mode. Tables 15.5 and 15.7 show the maximum bit rates with external clock
input.
Rev. 2.0, 08/02, page 350 of 788
Bit rate (bit/s)
BRR setting for baud rate generator (0
Operating frequency (MHz)
Determined by the SMR settings shown in the following table.
CKS1
0
0
1
1
Bit Rate Register (BRR)
SMR Setting
CKS0
0
1
0
1
Bit Rate
B =
B =
n
0
1
2
3
64
64
2
2
Ø
Ø
2n-1
2n-1
10
10
(N+1)
(N+1)
N
6
6
255)
Error
Error (%) = {
—
B
64
Ø
2
10
2n-1
6
(N+1)
- 1 }
100
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