HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 173

• Manufacturer Part Number: HD6432160
• Description: Hitachi 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

6.7
When this LSI accesses the external address space, it can insert a 1-state idle cycle (T
bus cycles when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is
possible, for example, to avoid data collisions between ROM with a long output floating time, and
high-speed memory and I/O interfaces.
If an external write occurs after an external read while the ICIS0 bit is set to 1 in BCR, an idle
cycle is inserted at the start of the write cycle.
Figure 6.16 shows examples of idle cycle operation. In these examples, bus cycle A is a read cycle
for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In figure 6.16 (a),
with no idle cycle inserted, a collision occurs in bus cycle B between the read data from ROM and
the CPU write data. In figure 6.16 (b), an idle cycle is inserted, thus preventing data collision.
Table 6.5 shows the pin states in an idle cycle.
Table 6.5
Pins
A23 to A0, ,26
D15 to D0
$6
5'
+:5, /:5
Address bus
Idle Cycle
Data bus
,
Pin States in Idle Cycle
Ø
(a) No idle cycle insertion
T
1
Bus cycle A
Long output floating time
Figure 6.16 Examples of Idle Cycle Operation
T
2
T
3
Bus cycle B
T
1
T
2
Data collision
Pin State
Contents of immediately following bus cycle
High impedance
High
High
High
Address bus
Data bus
,
Ø
T
1
Bus cycle A
Rev. 2.0, 08/02, page 133 of 788
T
(b) Idle cycle insertion
2
T
3
T
I
Bus cycle B
T
1
I
) between
T
2