HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 813

• Manufacturer Part Number: HD6432160
• Description: Hitachi 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Item
14.4.1 Watchdog Timer
Mode
Figure 14.2 Watchdog
Timer Mode (RST/10, =
1) Operation
14.6 Usage Notes
14.6.7 OVF Flag Clear
Condition
Section 15 Serial
Communication Interface
(SCI and IrDA)
15.1 Features
15.3.2 Receive Data
Register (RDR)
15.3.3 Transmit Data
Register (TDR)
16.3.5 I
Register (ICCR)
2
C Bus Control
Page
333
338
339
340
342
342
406
Corrected.
(Error)
(Error)
(Error)
Revisions (See Manual for Details)
Deleted.
(Correction)
Deleted.
A block diagram of SCI_1 is shown in figure 15.1.
(Correction)
A block diagram of the SCI is shown in figure 15.1.
Description added.
After confirming that the RDRF bit in SSR is set to 1, read
RDR for only once. RDR cannot be written to by the CPU.
RDR is initialized to H'00.
Description added.
Although TDR can be read from or written to by the CPU at all
times, to achieve reliable serial transmission, write transmit
data to TDR for only once after confirming that the TDRE bit in
SSR is set to 1. TDR is initialized to H'FF.
assuming that the start condition has been issued.
(Correction)
assuming that the stop condition has been issued.
Internal reset signal
Module stop mode availability
Note * After the OVF bit becomes 1, it is cleared to 0 by an internal reset.
WT/
TME
OVF
signal
H'FF
H'00
: Timer mode select bit
: Timer enable bit
: Overflow flag
The XRST bit is also cleared to 0.
TCNT value
WT/
TME = 1
= 1
Write H'00 to
TCNT
Rev. 2.0, 08/02, page 773 of 788
and internal reset signals generated
132 system clocks
518 system clocks
Overflow
OVF = 1*
WT/
TME = 1
= 1
Write H'00 to
TCNT
Time