HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 30

• Manufacturer Part Number: HD6432160
• Description: Hitachi 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 16.14 Sample Flowchart for Operations in Master Receive Mode
Figure 16.15 Sample Flowchart for Operations in Master Receive Mode
Figure 16.16 Example of Master Receive Mode Operation Timing
Figure 16.17 Example of Stop Condition Issuance Timing in Master Receive Mode
Figure 16.18 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1)................438
Figure 16.19 Example of Slave Receive Mode Operation Timing (1) (MLS = 0, HNDS= 1)....440
Figure 16.20 Example of Slave Receive Mode Operation Timing (2) (MLS = 0, HNDS= 1)...440
Figure 16.21 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0)................441
Figure 16.22 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0).......443
Figure 16.23 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0).......443
Figure 16.24 Sample Flowchart for Slave Transmit Mode .........................................................444
Figure 16.25 Example of Slave Transmit Mode Operation Timing (MLS = 0)..........................446
Figure 16.26 IRIC Setting Timing and SCL Control (1).............................................................447
Figure 16.27 IRIC Setting Timing and SCL Control (2).............................................................448
Figure 16.28 IRIC Setting Timing and SCL Control (3).............................................................449
Figure 16.29 Block Diagram of Noise Canceler .........................................................................452
Figure 16.30 Notes on Reading Master Receive Data ................................................................458
Figure 16.31 Flowchart for Start Condition Issuance Instruction for Retransmission
Figure 16.32 Stop Condition Issuance Timing............................................................................460
Figure 16.33 IRIC Flag Clearing Timing When WAIT = 1........................................................460
Figure 16.34 ICDR Read and ICCR Access Timing in Slave Transmit Mode ...........................461
Figure 16.35 TRS Bit Set Timing in Slave Mode .......................................................................462
Section 17 Keyboard Buffer Controller
Figure 17.1 Block Diagram of Keyboard Buffer Controller .......................................................465
Figure 17.2 Keyboard Buffer Controller Connection..................................................................466
Figure 17.3 Sample Receive Processing Flowchart ....................................................................471
Figure 17.4 Receive Timing........................................................................................................472
Figure 17.5 (1) Sample Transmit Processing Flowchart .............................................................473
Figure 17.5 (2) Sample Transmit Processing Flowchart .............................................................474
Figure 17.6 Transmit Timing ......................................................................................................474
Figure 17.7 (1) Sample Receive Abort Processing Flowchart ....................................................475
Figure 17.7 (2) Sample Receive Abort Processing Flowchart ....................................................476
Figure 17.8 Receive Abort and Transmit Start (Transmission/Reception Switchover) Timing..476
Figure 17.9 KCLKI and KDI Read Timing ................................................................................477
Figure 17.10 KCLKO and KDO Write Timing ..........................................................................477
Figure 17.11 KBF Setting and KCLK Automatic I/O Inhibit Generation Timing......................478
Figure 17.12 Receive Counter and KBBR Data Load Timing....................................................479
Rev. 2.0, 08/02, page xxviii of xxxviii
(receiving multiple bytes) (WAIT = 1) ..................................................................433
(receiving a single byte) (WAIT = 1) .....................................................................434
(MLS = ACKB = 0, WAIT = 1).............................................................................436
(MLS = ACKB = 0, WAIT = 1).............................................................................437
and Timing .............................................................................................................459