HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 350

• Manufacturer Part Number: HD6432160
• Description: Hitachi 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

13.4.2
The timer connection facility and TMR_X can be used to generate signals with different duty
cycles and rising/falling edges (clamp waveforms) in synchronization with the input signal (IHI
signal). Three clamp waveforms can be generated: the CL1, CL2, and CL3 signals. In addition, the
CL4 signal can be generated using TMR_Y.
The CL1 signal rises simultaneously with the rise of the IHI signal, and when the CL1 signal is
high, the CL2 signal rises simultaneously with the fall of the IHI signal. The fall of both the CL1
and CL2 signals can be specified by TCORA. The rise of the CL3 signal can be specified as
simultaneous with the sampling of the fall of the IHI signal using the system clock, and the fall of
the CL3 signal can be specified by TCORC. The CL3 signal can also fall when the IHI signal
rises.
TCNT in TMR_X is set to count internal clock pulses and to be cleared on the rising edge of the
external reset signal (IHI signal).
The value to be used as the CL1 signal pulse width is written in TCORA. Write a value of H'02 or
more in TCORA when internal clock ø is selected as the TMR_X counter clock, and a value or
H'01 or more when ø/2 is selected. When internal clock ø is selected, the CL1 signal pulse width is
(TCORA set value + 3
pulse width is greater than the IHI signal pulse width.
The value to be used as the CL3 signal pulse width is written in TCORC. TICR in TMR_X
captures the value of TCNT at the inverse of the external reset signal edge (in this case, the falling
edge of the IHI signal). The timing of the fall of the CL3 signal is determined by the sum of the
contents of TICR and TCORC. Caution is required if the rising edge of the IHI signal precedes the
fall timing set by the contents of TCORC, since the IHI signal will cause the CL3 signal to fall.
Rev. 2.0, 08/02, page 310 of 788
IHI signal
PDC signal
TCORB
(threshold)
TCNT
Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation)
Counter reset
caused by
IHI signal
Figure 13.2 Timing Chart for PWM Decoding
0.5). When the CL2 signal is used, the setting must be made so that this
IHI signal is tested
at compare-match
Counter clear
caused by
TCNT overflow
At the 2nd compare-match,
IHI signal is not tested