HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 496

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HD6432160

Manufacturer Part Number
HD6432160
Description
Hitachi 16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
6. The I
Rev. 2.0, 08/02, page 456 of 788
and 300 ns. The I
table 16.9. However, because of the rise and fall times, the I
not be satisfied at the maximum transfer rate. Table 16.11 shows output timing calculations for
different operating frequencies, including the worst-case influence of rise and fall times.
t
to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a
stop condition and issuance of a start condition, or (b) to select devices whose input timing
permits this output timing for use as slave devices connected to the I
t
specifications for worst-case calculations of t
include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load,
(b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input
timing permits this output timing for use as slave devices connected to the I
BUFO
SCLLO
fails to meet the I
2
in high-speed mode and t
C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
2
C bus interface SCL and SDA output timing is prescribed by t
2
C bus interface specifications at any frequency. The solution is either (a)
STASO
in standard mode fail to satisfy the I
Sr
/t
Sf
. Possible solutions that should be investigated
2
C bus interface specifications may
2
C bus.
2
C bus interface
2
C bus.
cyc
, as shown in

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