HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 515

• Manufacturer Part Number: HD6432160
• Description: Hitachi 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

17.4.3
This LSI (system side) can forcibly abort transmission from the device connected to it (keyboard
side) in the event of a protocol error, etc. In this case, the system holds the clock low. During
reception, the keyboard also outputs a clock for synchronization, and the clock is monitored when
the keyboard output clock is high. If the clock is low at this time, the keyboard judges that there is
an abort request from the system, and data transmission from the keyboard is aborted. Thus the
system can abort reception by holding the clock low for a certain period. A sample receive abort
processing flowchart is shown in figure 17.7, and the receive abort timing in figure 17.8.
Receive Abort
Disable receive abort
RXCR3 to RXCR0
Receive state
Read KBCRH
Read KBCRL
KBF = 0?
requests
Figure 17.7 (1) Sample Receive Abort Processing Flowchart
B'1001?
Start
Yes
Yes
[3]
No
No
and clear receive counter)
(disable KBBR reception
(receive abort request)
command transmission
To transmit operation
Clear I/O inhibit
Transmit data
(KCLKO = 1)
Processing 1
KCLKO = 0
Set start bit
(KDO = 0)
Retransmit
KBE = 0
(data)?
Yes
[1]
[2]
No
[1] Read KBCRL, and if KBF = 1,
[2] Read KBCRH, and if the value of
[3] If the value of bits RXCR3 to
perform processing 1.
bits RXCR3 to RXCR0 is less than
B'1001, write 0 in KCLKO to abort
reception.
If the value of bits RXCR3 to
RXCR0 is B'1001 or greater, wait
until stop bit reception is
completed, then perform receive
data processing, and proceed to
the next operation.
RXCR0 is B'1001 or greater, the
parity bit is being received. With
the PS2 interface, a receive abort
request following parity bit
reception is disabled. Wait until
stop bit reception is completed,
perform receive data processing
and clear the KBF flag, then
proceed to the next operation.
Rev. 2.0, 08/02, page 475 of 788
and clear receive counter)
(disable KBBR reception
(enable KB operation)
To receive operation
Clear I/O inhibit
(KCLKO = 1)
KBE = 0
KBE = 1