HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 132

• Manufacturer Part Number: HD6432160
• Description: Hitachi 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

5.3.6
The ISR register is a flag register that indicates the status of IRQ7 to IRQ0 interrupt requests.
Bit
7
6
5
4
3
2
1
0
Notes: 1. When a product, in which a DTC is incorporated, is used, the corresponding flag bit is
5.3.7
The KMIMRA, KMIMR, and WUEMRB registers enable or disable key-sensing interrupt inputs
(.,148 to .,13), and wake-up event interrupt inputs (:8(: to :8(3).
Bit
7
6
5
4
3
2
1
0
Rev. 2.0, 08/02, page 92 of 788
KMIMRA
2. Only 0 can be written, for flag clearing.
Bit Name
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
Bit Name
KMIMR15
KMIMR14
KMIMR13
KMIMR12
KMIMR11
KMIMR10
KMIMR9
KMIMR8
IRQ Status Register (ISR)
Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR)
Wake-Up Event Interrupt Mask Register (WUEMRB)
not automatically cleared even when exception handing is executed. For details, refer to
section 5.8.4, Setting on a Product Incorporating DTC.
Initial Value
0
0
0
0
0
0
0
0
Initial Value
1
1
1
1
1
1
1
1
R/W
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2
2
2
2
2
2
2
2
Description
[Setting condition]
When the interrupt source selected by the ISCR
registers occurs
[Clearing conditions]
Description
Keyboard Matrix Interrupt Mask 15 to 8
These bits enable or disable a key-sensing
input interrupt request (KIN15 to KIN8).
0: Enables a key-sensing input interrupt request
1: Disables a key-sensing input interrupt
request
When reading IRQnF flag when IRQnF = 1,
then writing 0 to IRQnF flag
When interrupt exception handling is
executed when low-level detection is set
and ,54Q input is high
When IRQn interrupt exception handling is
executed when falling-edge, rising-edge, or
both-edge detection is set*
1
(n = 7 to 0)*
1