HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 567
HD6432160
Manufacturer Part Number
HD6432160
Description
Hitachi 16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6432160.pdf
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19.3.8
The SIRQCR registers contain status bits that indicate the SERIRQ operating mode and bits that
specify SERIRQ interrupt sources.
Bit
7
6
5
SIRQCR0
Bit Name Initial Value Slave Host Description
Q/&
SELREQ 0
IEDIR
SERIRQ Control Registers 0 and 1 (SIRQCR0, SIRQCR1)
0
0
R
R/W
R/W
R/W
—
—
—
Quiet/Continuous Mode Flag
Indicates the mode specified by the host at the end
of an SERIRQ transfer cycle (stop frame).
0: Continuous mode
[Clearing conditions]
1: Quiet mode
[Setting condition]
Start Frame Initiation Request Select
Selects whether start frame initiation is requested
when one or more interrupt requests are cleared, or
when all interrupt requests are cleared, in quiet
mode.
0: Start frame initiation is requested when all
interrupt requests are cleared in quiet mode.
1: Start frame initiation is requested when one or
more interrupt requests are cleared in quiet mode.
Specifies whether LPC channel 2 and channel 3
SERIRQ interrupt source (SMI, IRQ6, IRQ9 to
IRQ11) generation is conditional upon OBF, or is
controlled only by the host interrupt enable bit.
0: Host interrupt is requested when host interrupt
enable bit and corresponding OBF are both set to 1
1: Host interrupt is requested when host interrupt
enable bit is set to 1
Interrupt Enable Direct Mode
LPC hardware reset, LPC software reset
Specification by SERIRQ transfer cycle stop
frame
Specification by SERIRQ transfer cycle stop
frame.
Rev. 2.0, 08/02, page 527 of 788
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