AM79C970A Advanced Micro Devices, AM79C970A Datasheet
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AM79C970A
Manufacturer Part Number
AM79C970A
Description
PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
Manufacturer
Advanced Micro Devices
Datasheet
1.AM79C970A.pdf
(219 pages)
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Am79C970A
PCnet
for PCI Local Bus Product
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
The 32-bit PCnet-PCI II single-chip full-duplex Ethernet
controller is a highly integrated Ethernet system solution
designed to address high-performance system applica-
tion requirements. It is a flexible bus-mastering device
that can be used in any application, including network-
ready PCs, printers, fax modems, and bridge/router de-
This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended
to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
Single-chip Ethernet controller for the Periph-
eral Component Interconnect (PCI) local bus
Supports ISO 8802-3 (IEEE/ANSI 802.3) and
Ethernet standards
Direct interface to the PCI local bus (Revision
2.0 compliant)
High-performance 32-bit Bus Master architec-
ture with integrated DMA buffer Management
Unit for low CPU and bus utilization
Software compatible with AMD PCnet Family,
LANCE/C-LANCE, and Am79C900 ILACC regis-
ter and descriptor architecture
Compatible with PCnet Family driver software
Full-duplex operation for increased network
bandwidth
Big endian and little endian byte alignments
supported
3.3 V/5 V signaling for PCI bus interface
Low-power CMOS design with two sleep
modes allows reduced power consumption for
critical battery powered applications and Green
PCs
Integrated Magic Packet
wake up of Green PCs
Individual 272-byte transmit and 256-byte re-
ceive FIFOs provide frame buffering for in-
creased system latency and support the
following features:
— Automatic retransmission with no FIFO reload
— Automatic receive stripping and transmit pad-
— Automatic runt frame rejection
— Automatic selection of received collision frames
Microwire EEPROM interface supports
jumperless design and provides through-chip
programming
ding (individually programmable)
PRELIMINARY
TM
-PCI II Single-Chip Full-Duplex Ethernet Controller
TM
support for remote
signs. The bus-master architecture provides high data
throughput in the system and low CPU and system bus
utilization. The PCnet-PCI II controller is fabricated with
AMD’s advanced low-power CMOS process to
provide low operating and standby current for power
sensitive applications.
Supports optional Boot PROM for diskless
node applications
Look-Ahead Packet Processing (LAPP) data
handling technique reduces system overhead
by allowing protocol analysis to begin before
end of receive frame
Integrated Manchester Encoder/Decoder
Provides Integrated Attachment Unit Interface
(AUI) and 10BASE-T transceiver with automatic
port selection
Automatic Twisted-Pair receive polarity detec-
tion and automatic correction of the receive
polarity
Optional byte padding to long-word boundary
on receive
Dynamic transmit FCS generation programma-
ble on a frame-by-frame basis
Internal/external loopback capabilities
Supports the following types of network inter-
faces:
— AUI to external 10BASE2, 10BASE5,
— Internal 10BASE-T transceiver with Smart
JTAG Boundary Scan (IEEE 1149.1) test access
port interface and NAND Tree test mode for
board-level production connectivity test
Supports LANCE General Purpose Serial Inter-
face (GPSI)
Supports External Address Detection Interface
(EADI)
4 programmable LEDs for status indication
132-pin PQFP package
10BASE-T or 10BASE-F MAU
Squelch to Twisted-Pair medium
Publication# 19436
Issue Date: April 1995
Rev. A
Advanced
Devices
Amendment /+1
Micro