AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 126

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

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AMD
DXMTFCS
LOOP
DTX
Read/Write
when either the STOP or the
SPND bit is set.
Disable Transmit CRC (FCS).
When DXMTFCS is cleared to
ZERO,
generate and append an FCS to
the transmitted frame. When
DXMTFCS is set to ONE, no FCS
is generated or sent with the
transmitted frame. DXMTFCS is
overridden when ADD_FCS is
set in TMD1.
If
ADD_FCS is clear for a particular
frame, no FCS will be generated.
The value of ADD_FCS is valid
only when STP is set in TMD1. If
ADD_FCS is set for a particular
frame, the state of DXMTFCS is
ignored and a FCS will be ap-
pended on that frame by the
transmit circuitry. See also the
ADD_FCS bit in TMD1.
This bit is called DTCR in the
C-LANCE (Am79C90).
Read/Write
when either the STOP or the
SPND bit is set.
Loopback
PCnet-PCI II controller to oper-
ate in full-duplex mode for test
purposes. The setting of the
full-duplex control bits in BCR9
have no effect when the device
operates in loopback mode.
When LOOP is set to ONE,
loopback is enabled. In combina-
tion with INTL and MENDECL,
various loopback modes are
defined
Configuration table.
Read/Write
when either the STOP or the
SPND bit is set. LOOP is cleared
by H_RESET or S_RESET and is
unaffected
STOP bit.
Disable Transmit. When DTX is
set to ONE, the PCnet-PCI II con-
troller will not access the transmit
descriptor ring and therefore no
transmissions are attempted.
When DTX is cleared to ZERO,
TXON (CSR0, bit 4) is set to ONE
after STRT (CSR0, bit 1) has
been set to ONE.
Read/Write
when either the STOP or the
SPND bit is set.
DXMTFCS
the
in
by
accessible
accessible
Enable
accessible
accessible
transmitter
the
is
setting
set
Loopback
P R E L I M I N A R Y
allows
only
only
only
only
Am79C970A
and
the
will
0
CSR16: Initialization Block Address Lower
Bit
31–16 RES
15–0
CSR17: Initialization Block Address Upper
Bit
31–16 RES
15–0 IADRH
CSR18: Current Receive Buffer Address Lower
Bit
31–16 RES
15–0 CRBAL
CSR19: Current Receive Buffer Address Upper
Bit
31–16 RES
IADRL
Name
Name
Name
Name
DRX
Disable Receiver. When DRX is
set to ONE, the PCnet-PCI II con-
troller will not access the receive
descriptor ring and therefore all
receive frame data are ignored.
When DRX is cleared to ZERO,
RXON (CSR0, bit 5) is set to
ONE after STRT (CSR0, bit 1)
has been set to ONE.
Read/Write
when either the STOP or the
SPND bit is set.
Description
Reserved locations. Written as
ZEROs and read as undefined.
This register is an alias of CSR1.
Read/Write
when either the STOP or the
SPND bit is set.
Description
Reserved locations. Written as
ZEROs and read as undefined.
This register is an alias of CSR2.
Read/Write
when either the STOP or the
SPND bit is set.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the lower 16 bits of the
current receive buffer address at
which the PCnet-PCI II controller
will store incoming frame data.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
accessible
accessible
accessible
accessible
only
only
only
only