AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 41

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

During the data phase of an I/O write, memory mapped
I/O write or configuration write command that selects
the PCnet-PCI II controller as target, the device samples
the AD[31:0] and C/BE[3:0] lines for parity on the clock
edge data is transferred. PAR is sampled in the follow-
ing clock cycle. If a parity error is detected and reporting
of that error is enabled by setting PERREN (PCI Com-
mand register, bit 6) to ONE, PERR is asserted one
clock later. The parity error will always set PERR (PCI
Status register, bit 15) to ONE even when PERREN is
cleared to ZERO. The PCnet-PCI II controller will finish
a transaction that has a data parity error in the normal
DEVSEL
FRAME
PERR
TRDY
C/BE
IRDY
CLK
PAR
AD
1
Figure 11. Slave Cycle Data Parity Error Response
2
ADDR
CMD
3
PAR
P R E L I M I N A R Y
4
Am79C970A
5
DATA
BE
way by asserting TRDY. The corrupted data will be writ-
ten to the addressed location.
Figure 11 shows a transaction that suffered a parity
error at the time data was transferred (clock 7, IRDY and
TRDY are both asserted). PERR is driven high at the
beginning of the data phase and then drops low due to
the parity error on clock 9, two clock cycles after the data
was transferred. After PERR is driven low, the
PCnet-PCI II controller drives PERR high for one clock
cycle, since PERR is a sustained tri-state signal.
6
PAR
7
8
9
10
19436A-14
AMD
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