AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 79

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

The number of bytes to be stripped is calculated from
the embedded length field (as defined in the ISO 8802-3
(IEEE/ANSI 802.3) definition) contained in the frame.
The length indicates the actual number of LLC data
bytes contained in the message. Any received frame
which contains a length field less than 46 bytes will have
Since any valid Ethernet Type field value will always be
greater than a normal 802.3 Length field ( 46), the
PCnet-PCI II controller will not attempt to strip valid
Ethernet frames. Note that for some network protocols,
the value passed in the Ethernet Type and/or 802.3
Length field is not compliant with either standard and
may cause problems if pad stripping is enabled.
Receive FCS Checking
Reception and checking of the received FCS is per-
formed automatically by the PCnet-PCI II controller.
Note that if the Automatic Pad Stripping feature is en-
abled, the FCS for padded frames will be verified
against the value computed for the incoming bit stream
including pad characters, but the FCS value for a pad-
ded frame will not be passed to the host. If an FCS error
is detected in any frame, the error will be reported in the
CRC bit in RMD1.
Receive Exception Conditions
Exception conditions for frame reception fall into two
Increasing Time
1010....1010
Preamble
Start of Frame
at Time = 0
Bits
56
10101011
SFD
Bits
8
Figure 35. 802.3 Frame And Length Field Transmission Order
Destination
Address
Bytes
6
P R E L I M I N A R Y
Bit
0
Am79C970A
Address
Source
Bytes
Significant
6
Most
Byte
the pad field stripped (if ASTRP_RCV is set). Receive
frames which have a length field of 46 bytes or greater
will be passed to the host unmodified.
The figure below shows the byte/bit ordering of the re-
ceived length field for an 802.3 compatible frame format.
distinct categories: those which are the result of normal
network operation, and those which occur due to abnor-
mal network and/or host related events.
Normal events which may occur and which are handled
autonomously by the PCnet-PCI II controller are basi-
cally collisions within the slot time and automatic runt
packet rejection. The PCnet-PCI II controller will ensure
that collisions which occur within 512 bit times from the
start of reception (excluding preamble) will be automati-
cally deleted from the receive FIFO with no host inter-
vention. The receive FIFO will delete any frame which is
composed of fewer than 64 bytes provided that the Runt
Packet Accept (RPA bit in CSR124) feature has not
been enabled and the network interface is operating in
half-duplex mode. This criterion will be met regardless
of whether the receive frame was the first (or only) frame
in the FIFO or if the receive frame was queued behind a
previously received message.
Bit
Length
7
Bytes
2
Bit
0
Significant
1 – 1500
Bytes
Least
Byte
Data
LLC
46 – 1500
Bytes
Bit
7
45 – 0
Bytes
Pad
Bytes
FCS
AMD
4
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