AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 110

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

6–0
PCI I/O Base Address Register (Offset 10h)
The PCI I/O Base Address register is a 32-bit register
that determines the location of the PCnet-PCI II control-
ler I/O resources in all of I/O space. It is located at offset
10h in the PCI Configuration Space.
31–5 IOBASE
4–2
1
0
110
AMD
IOSPACE
LAYOUT
IOSIZE
RES
PCI configuration space layout.
Read as ZEROs, write opera-
tions have no effect. The layout
of the PCI configuration space
locations 10h to 3Ch is as shown
in the table at the beginning of
this section.
I/O base address most signifi-
cant 27 bits. These bits are writ-
ten by the host to specify the
location of the PCnet-PCI II con-
troller I/O resources in all of I/O
space. IOBASE must be written
with a valid address before the
PCnet-PCI II controller slave I/O
mode is turned on by setting the
IOEN bit (PCI Command regis-
ter, bit 0).
When the PCnet-PCI II controller
is enabled for I/O mode (IOEN is
set), it monitors the PCI bus for
a valid I/O command. If the value
on AD[31:5] during the address
phase of the cycles matches
the
PCnet-PCI II controller will drive
DEVSEL indicating it will re-
spond to the access.
IOBASE is read and written by
the host. IOBASE is cleared by
H_RESET and is not affected by
S_RESET or by setting the
STOP bit.
I/O size requirements. Read as
ZEROs, write operations have
no effect.
IOSIZE indicates the size of the
I/O space the PCnet-PCI II con-
troller requires. When the host
writes a value of FFFF FFFFh to
the I/O Base Address register,
it will read back a value of ZERO
in bits 4–2. That indicates a
PCnet-PCI II controller I/O space
requirement of 32 bytes.
Reserved location. Read as
ZERO, write operations have
no effect.
I/O space indicator. Read as
ONE, write operations have no
effect. Indicating that this base
address register describes an I/O
base address.
value
of
IOBASE,
P R E L I M I N A R Y
Am79C970A
the
PCI Memory Mapped I/O Base Address Register
(Offset 14h)
The PCI Memory Mapped I/O Base Address register is a
32-bit register that determines the location of the
PCnet-PCI II controller I/O resources in all of memory
space. It is located at offset 14h in the PCI
Configuration Space.
Bit
31–5 MEMBASE
4
3
PREFETCH
MEMSIZE
Name
Description
Memory mapped I/O base ad-
dress most significant 27 bits.
These bits are written by the host
to specify the location of the
PCnet-PCI II controller I/O re-
sources in all of memory space.
MEMBASE must be written
with a valid address before the
PCnet-PCI II controller slave
memory mapped I/O mode is
turned on by setting the MEMEN
bit (PCI Command register,
bit 1).
When the PCnet-PCI II controller
is enabled for memory mapped
I/O mode (MEMEN is set), it
monitors the PCI bus for a valid
memory command. If the value
on AD[31:5] during the address
phase of the cycles matches the
value
PCnet-PCI II controller will drive
DEVSEL indicating it will re-
spond to the access.
MEMBASE is read and written by
the host. MEMBASE is cleared
by H_RESET and is not affected
by S_RESET or by setting the
STOP bit.
Memory mapped I/O size re-
quirements. Read as ZEROs,
write operations have no effect.
MEMSIZE indicates the size of
the
PCnet-PCI II controller requires.
When the host writes a value of
FFFF FFFFh to the Memory
Mapped I/O Base Address regis-
ter, it will read back a value of
ZERO in bit 4. That indicates a
PCnet-PCI II controller memory
space requirement of 32 bytes.
Prefetchable. Read as ZERO,
write operations have no effect.
Indicates that memory space
controlled by this base address
register is not prefetchable. Data
in the memory mapped I/O space
cannot be prefetched. Because
one of I/O resources in this
memory
of
MEMBASE,
space
the
the