AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 152

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

BCR9: Full-Duplex Control
Bit
31–16 RES
15–3
2
1
152
AMD
FDRPAD
AUIFD
Name
RES
inputs to the AUI or GPSI ports
within the first 4 s after every
transmission for the purpose of
SQE testing will not cause the
LEDOUT bit to be set.
Read/Write accessible always.
COLE is cleared by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
Description
Note that bits 15–0 in this register
are programmable through the
external EEPROM. Reserved
bits and read-only bits should be
programmed to ZERO.
Reserved locations. Written as
ZEROs and read as undefined.
Reserved locations. Written as
ZEROs and read as undefined.
Full-Duplex Runt Packet Accept
Disable. When FDRPAD is set to
ONE and full-duplex mode is en-
abled, the PCnet-PCI II controller
will only receive frames that meet
the minimum Ethernet frame
length of 64 bytes. Receive DMA
will not start until at least 64 bytes
or a complete frame have been
received. By default, FDRPAD is
cleared to ZERO. The PCnet-
PCI II controller will accept any
length frame and receive DMA
will start according to the pro-
gramming of the receive FIFO
watermark.
should not be any runt packets in
a full-duplex network, since the
main cause for runt packets is a
network collision and there are
no collisions in a full-duplex net-
work.
Read/Write accessible always.
FDRPAD
H_RESET and is not affected by
S_RESET or by setting the
STOP bit.
AUI full-duplex. AUIFD enables
full-duplex operation on the AUI
port. AUIFD is only meaningful if
FDEN (BCR9, bit 0) is set to
ONE. If the FDEN bit is ZERO,
the AUI port will always operate
in half-duplex mode. If FDEN is
set to ONE and AUIFD is set to
ONE, full-duplex operation on
is
Note
cleared
that
P R E L I M I N A R Y
there
Am79C970A
by
0
BCR16: I/O Base Address Lower
Bit
31–16 RES
15–5 IOBASEL
4–0
AUIFD
(bit 1)
X
0
1
FDEN
Name
RES
FDEN
(bit 0)
0
1
1
Effect on the
Half-Duplex
Half-Duplex
Full-Duplex
AUI Port
the
However, if FDEN is set to ONE
but the AUIFD bit is cleared to
ZERO, the AUI port will always
operate in half-duplex mode.
Read/Write accessible always.
AUIFD is cleared by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
Full-duplex Enable. FDEN en-
ables
When FDEN is set to ONE, the
PCnet-PCI II controller will oper-
ate in full-duplex mode when
either the 10BASE-T or the GPSI
port is enabled. To enable full-
duplex operation on the AUI port,
the AUIFD bit (BCR9, bit1) must
be set to ONE in addition to set-
ting FDEN to ONE. When the
DLNKTST bit (CSR15, bit 12) is
set to ONE, the 10BASE-T port
will operate in half-duplex mode
regardless of the setting of
FDEN.
Read/Write accessible always.
FDEN is cleared by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Reserved
H_RESET, the value of these
bits will be undefined. The
settings of these bits will have
no effect on any PCnet-PCI II
controller function. It is only in-
cluded for software compatibility
with other PCnet family devices.
Read/Write accessible always.
IOBASEL is not affected by
S_RESET or by setting the
STOP bit.
Reserved locations. Written as
ZEROs, read as undefined.
AUI
Effect on the
Half-Duplex
Full-Duplex
Full-Duplex
10BASE-T
full-duplex
Port
port
locations.
is
Effect on the
Half-Duplex
Full-Duplex
Full-Duplex
GPSI Port
operation.
enabled.
After