AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 133

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

CSR60: Previous Transmit Descriptor Address
Lower
Bit
31–16 RES
15–0 PXDAL
CSR61: Previous Transmit Descriptor Address
Upper
Bit
31–16 RES
15–0 PXDAU
SWSTYLE
All Other
[7:0]
00h
01h
02h
03h
Name
Name
PCnet-ISA
C-LANCE
Reserved
controller
PCnet-
PCnet-
ILACC
Name
PCI II
PCI II
Style
/
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the lower 16 bits of the
previous transmit descriptor ad-
dress pointer. The PCnet-PCI II
controller can stack multiple
transmit frames.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the upper 16 bits of the
previous transmit descriptor ad-
dress pointer. The PCnet-PCI II
controller can stack multiple
transmit frames.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
CSRPCNET
Undefined
1
0
1
1
accessible
accessible
Undefined Undefined
SSIZE32
0
1
1
1
Table 25. Software Styles
P R E L I M I N A R Y
structures, non-burst
or burst access
structures, non-burst
or burst access
structures, non-burst
or burst access
structures, non-burst
or burst access
16-bit software
32-bit software
32-bit software
32-bit software
only
only
Am79C970A
Block Entries
Initialization
CSR62: Previous Transmit Byte Count
Bit
31–16 RES
15–12 RES
11–0
CSR63: Previous Transmit Status
Bit
31–16 RES
15–0
PXBC
PXST
Name
Name
16-bit software
structures, non-burst
access only
32-bit software access
structures, non-burst
access only
32-bit software
structures, non-burst
access only
32-bit software
structures, non-burst
or burst access
Undefined
Descriptor Ring
Entries
Description
Reserved locations. Written as
ZEROs and read as undefined.
Reserved locations.
Previous Transmit Byte Count.
This field is a copy of the BCNT
field of TMD1 of the previous
transmit descriptor.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Previous Transmit Status. This
field is a copy of bits 31–16 of
TMD1 of the previous transmit
descriptor.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
All bits in CSR4
are used, TMD1[29]
is ADD_FCS
CSR4[9:8],CSR4[5:4]
and CSR4[1:0] have
no function, TMD1[29]
is NO_FCS.
All bits in CSR4 are
used, TMD1[29] is
ADD_FCS
All bits in CSR4 are
used, TMD1[29] is
ADD_FCS
Undefined
Interpretations
accessible
accessible
Altered Bit
AMD
only
only
133