AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 109

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

7
6–0
PCI Revision ID Register (Offset 08h)
The PCI Revision ID register is an 8-bit register that
specifies the PCnet-PCI II controller revision number.
The value of this register is 1xh, with the lower four bits
being silicon-revision dependent.
The PCI Revision ID register is located at offset 08h in
the PCI Configuration Space. It is read only.
PCI Programming Interface Register (Offset 09h)
The PCI Programming Interface register is an 8-bit reg-
ister that identifies the programming interface of
PCnet-PCI II controller. PCI does not define any specific
register-level programming interfaces for network de-
vices. The value of this register is 00h.
The PCI Programming Interface register is located at
offset 09h in the PCI Configuration Space. It is read only.
PCI Sub-Class Register (Offset 0Ah)
The PCI Sub-Class register is an 8-bit register that iden-
tifies specifically the function of the PCnet-PCI II control-
ler. The value of this register is 00h which identifies the
PCnet-PCI II controller device as an Ethernet controller.
The PCI Sub-Class register is located at offset 0Ah in
the PCI Configuration Space. It is read only.
FBTBC
RES
data parity error and the Parity
Error Response enable bit (PCI
Command register, bit 6) is set.
During the data phase of all
memory read commands, the
PCnet-PCI II controller checks
for parity error by sampling the
AD[31:0] and C/BE[3:0] and the
PAR lines. During the data phase
of all memory write commands,
the
checks the PERR input to detect
whether the target has reported a
parity error.
DATAPERR is set by the PCnet-
PCI II controller and cleared by
writing a ONE. Writing a ZERO
has no effect. DATAPERR is
cleared by H_RESET and is not
affected by S_RESET or by set-
ting the STOP bit.
Fast Back-To-Back Capable.
Read as ONE, write operations
have no effect. The PCnet-PCI II
controller is capable of accepting
fast back-to-back transactions
with the first transaction address-
ing a different target.
Reserved locations. Read as
ZERO, write operations have
no effect.
PCnet-PCI
II
controller
P R E L I M I N A R Y
Am79C970A
PCI Base-Class Register (Offset 0Bh)
The PCI Base-Class register is an 8-bit register that
broadly classifies the function of the PCnet-PCI II
controller. The value of this register is 02h which
classifies the PCnet-PCI II controller device as a
network controller.
The PCI Base-Class register is located at offset 0Bh in
the PCI Configuration Space. It is read only.
PCI Latency Timer Register (Offset 0Dh)
The PCI Latency Timer register is an 8-bit register that
specifies
PCnet-PCI II controller will control the bus once it starts
its bus mastership period. The time is measured in clock
cycles. Every time the PCnet-PCI II controller asserts
FRAME at the beginning of a bus mastership period, it
will copy the value of the PCI Latency Timer register into
a counter and start counting down. The counter will
freeze at ZERO. When the system arbiter removes GNT
while the counter is non-ZERO, the PCnet-PCI II con-
troller will continue with its data transfers. It will only re-
lease the bus when the counter has reached ZERO.
The PCI Latency Timer is only significant in burst trans-
actions, where FRAME stays asserted until the last data
phase. In a non-burst transaction, FRAME is only
asserted during the address phase. The internal latency
counter will be cleared and suspended while FRAME
is deasserted.
All 8 bits of the PCI Latency Timer register are program-
mable. The host should read the PCnet-PCI II controller
PCI MIN_GNT and PCI MAX_LAT registers to
determine the latency requirements for the device and
then initialize the Latency Timer register with an
appropriate value.
The PCI Latency Timer register is located at offset 0Dh
in the PCI Configuration Space. It is read and written by
the host. The PCI Latency Timer register is cleared by
H_RESET and is not effected by S_RESET or by setting
the STOP bit.
PCI Header Type Register (Offset 0Eh)
The PCI Header Type register is an 8-bit register that
describes the format of the PCI Configuration Space lo-
cations 10h to 3Ch and that identifies a device to be sin-
gle or multi function. The PCI Header Type register is
located at address 0Eh in the PCI Configuration Space.
It is read only.
Bit
7
FUNCT
Name
the
minimum
Description
Single function/multi function de-
vice. Read as ZERO, write op-
erations have no effect. The
PCnet-PCI II controller is a single
function device.
guaranteed
time
AMD
109
the