AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 138

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

15–12 RES
11–0 DMABC
CSR88: Chip ID Register Lower
Bit
31 – 28 VER
27 – 12PARTID
11 – 1 MANFID
0
138
AMD
Name
ONE
Reserved locations. Read and
written with ONEs.
DMA Byte Count Register. Con-
tains the two’s complement of the
remaining size of the current
transmit or receive buffer in
bytes. This register is incre-
mented by the Bus Interface Unit.
The DMABC register is unde-
fined until written.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Version. This 4-bit pattern is sili-
con-revision dependent.
Read accessible always. VER is
read
are ignored.
Part number. The 16-bit code for
the PCnet-PCI II controller is
0010 0110 0010 0001b (2621h).
This register is exactly the same
as the Device ID register in the
JTAG description. It is, however,
different from the ID stored in
the Device ID register in the PCI
configuration space.
Read accessible always. PAR-
TID is read only. Write operations
are ignored.
Manufacturer ID. The 11-bit
manufacturer code for AMD is
00000000001b. This code is per
the JEDEC Publication 106-A.
Note that this code is not the
same as the Vendor ID in the PCI
configuration space.
Read
MANFID is read only. Write op-
erations are ignored.
Always a logic ONE.
Read accessible always. ONE is
read
are ignored.
only.
only.
accessible
Write
Write
accessible
operations
operations
P R E L I M I N A R Y
always.
only
Am79C970A
CSR89: Chip ID Register Upper
Bit
31 – 16 RES
15 – 12 VER
11 – 0PARTIDU
CSR94: Transmit Time Domain Reflectometry
Count
Bit
31–16 RES
15–10 RES
9–0
CSR100: Bus Timeout
Bit
31–16 RES
15–0 MERRTO
XMTTDR
Name
Name
Name
Description
Reserved
as undefined.
Version. This 4-bit pattern is sili-
con-revision dependent.
Read accessible always. VER is
read
are ignored.
Upper 12 bits of the PCnet-PCI II
controller part number. I.e. 0010
0110 0010b.
Read
PARTIDU is read only. Write op-
erations are ignored.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Reserved locations. Read and
written as ZEROs.
Time Domain Reflectometry re-
flects the state of an internal
counter that counts from the start
of transmission to the occurrence
of loss of carrier. TDR is incre-
mented at a rate of 10 MHz.
Read accessible only when
either the STOP or the SPND bit
is set. Write operations are ig-
nored. XMTTDR is cleared by
H_RESET or S_RESET.
Description
Reserved locations. Written as
ZEROs and read as undefined.
This register contains the value
of the longest allowable bus la-
tency (interval between assertion
of REQ and assertion of GNT)
that a system may insert into a
PCnet-PCI II controller master
transfer. If this value of bus la-
tency is exceeded, then MERR
only.
accessible
locations.
Write
operations
always.
Read