AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 216

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

LIST OF REGISTER BIT CHANGES
PCI Configuration Space
Command Register
Status Register
Revision ID Register
Latency Timer Register
I/O Base Address Register
Memory Mapped I/O Base Address Register
Expansion ROM Base Address Register
Interrupt Line Register
MIN_GNT Register
MAX_LAT Register
E-2
Pin to disable external transceiver or DC-to-DC
converter. Polarity of assertion state
programmable.
ADSTEP (bit 7) now hardwired to ZERO. Was
hardwired to ONE.
MEMEN (bit 1) now read/write accessible. Was
hardwired to ZERO.
PERR (bit 15) now cleared by H_RESET. Was not
effected by H_RESET.
SERR (bit 14) now cleared by H_RESET. Was not
effected by H_RESET.
RMABORT (bit 13) now cleared by H_RESET.
Was not effected by H_RESET.
RTABORT (bit 12) now cleared by H_RESET. Was
not effected by H_RESET.
STABORT (bit 11) now cleared by H_RESET. Was
not effected by H_RESET.
DATAPERR (bit 8) now cleared by H_RESET.
Was not effected by H_RESET.
FBTBC (bit 7) now hardwired to ONE. Was hard-
wired to ZERO.
This 8-bit register is now hardwired to 1xh. It was
hardwired to 0xh.
This 8-bit register is now read/write accessible.
Was hardwired to ZERO.
IOBASE (bits 31–5) now cleared by H_RESET.
Was not effected by H_RESET.
New 32-bit register. Was reserved, read as ZERO,
writes have no effect.
New 32-bit register. Was reserved, read as ZERO,
writes have no effect.
This 8-bit register is now cleared by H_RESET.
Was not effected by H_RESET.
New 8-bit register. Was reserved, read as ZERO,
writes have no effect.
New 8-bit register. Was reserved, read as ZERO,
writeshave no effect.
AMD
Am79C970A
Control And Status Registers
CSR0: PCnet-PCI II controller Control and Status
Register
CSR3: Interrupt Masks and Deferral
Control
CSR4: Test and Features Control
CSR5:
In addition to the existing interrupt flags, INTR (bit
7), the interrupt summary bit, is also affected by
the new interrupt flags Excessive Deferral Interrupt
(EXDINT), Magic Packet Interrupt (MPINT) Sleep
Interrupt (SLPINT), System Interrupt (SINT) and
User Interrupt (UINT).
New bit: DXSUFLO (bit 6), Disable Transmit Stop
on Underflow error. Was reserved location, read
and written as ZERO.
New bit: UINTCMD (bit 7), User Interrupt Com-
mand. Was reserved location, read and written
as ZERO.
New bit: UINT (bit 6), User Interrupt. Was reserved
location, read as ZERO, written as ONE or ZERO.
New bit: TOKINTD (bit 15), Transmit OK Interrupt
Disable. Was reserved location, read and written
as ZERO.
New bit: LTINTEN (bit 14), Last Transmit Interrupt
Enable. Was reserved location, read and written as
ZERO.
New bit: SINT (bit 11), System Interrupt. Was re-
served location, read and written as ZERO.
New bit: SINTE (bit 10), System Interrupt Enable.
Was reserved location, read and written as ZERO.
New bit: SLPINT (bit 9), Sleep Interrupt. Was re-
served location, read and written as ZERO.
New bit: SLPINTE (bit 8), Sleep Interrupt Enable.
Was reserved location, read and written as ZERO.
New bit: EXDINT (bit 7), Excessive Deferral Inter-
rupt. Was reserved location, read and written as
ZERO.
New bit: EXDINTE (bit 6), Excessive Deferral Inter-
rupt Enable. Was reserved location, read and writ-
ten as ZERO.
New bit: MPPLBA (bit 5), Magic Packet Physical
Logical Broadcast Accept. Was reserved location,
read and written as ZERO.
New bit: MPINT (bit 4), Magic Packet Interrupt.
Was reserved location, read and written as ZERO.
New bit: MPINTE (bit 3), Magic Packet Interrupt
Enable. Was reserved location, read and written as
ZERO.
New bit: MPEN (bit 2), Magic Packet Enable. Was
reserved location, read and written as ZERO.