AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 218

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

BCR17: I/O Base Address Upper
BCR18: Burst Size and Bus Control
BCR20: Software Style
BCR21: Interrupt Control
E-4
This register is no longer programmable through
the EEPROM. The register is reserved and has no
effect on the operation of the device. It is only used
in the PCnet-32.
New bits: ROMTMG (bits 15–12), Expansion ROM
Timing. Was reserved location, read and written as
ZERO.
New bit: MEMCMD (bit 9), Memory Command.
Was reserved location, read and written as ZERO.
New bit: EXTREQ (bit 8), Extended Request. Was
reserved location, read and written as ONE.
BREADE (bit 6), Burst Read Enable. Extended
functionality of bit. Besides enabling burst read
accesses to the transmit buffer, BREADE will now
also enable burst read accesses to the initialization
block and, if SWSTYLE = 3, to the descriptor
ring entries.
BWRITE (bit 5), Burst Write Enable. Extended
functionality of bit. Besides enabling burst write
accesses to the receive buffer, BWRITE will now
also enable burst write accesses to the descriptor
ring entries, if SWSTYLE = 3.
LINBC (bits 2–0), Linear Burst Count. These bits
are now reserved and have no effect on the opera-
tion of the device.
New bit: APERREN (bit 10), Advanced Parity Error
Handling Enable. Was reserved location, read and
written as ZERO.
SWSTYLE (bits 7–0), Software Style. New option,
value of THREE selects new PCnet-PCI controller
style that reorders 32-bit descriptor entries to allow
burst accesses.
This register is no longer programmable through
the EEPROM. The register is reserved and has no
effect on the operation of the device. It is only used
in the PCnet-32.
AMD
Am79C970A
BCR22: PCI Latency
Receive Descriptor
RMD1
Transmit Descriptor
TMD1
New register. Was reserved location, read and
written as ZERO.
New bit: BPE (bit 23), Bus Parity Error. This bit is
active only if 32-bit software structures are used
for the descriptor ring entries (SWSTYLE = ONE,
TWO or THREE) and if APERREN (BCR20, bit 10)
is set to ONE. Was reserved location, read and
written as ZERO.
New bit: PAM (bit 22), Physical Address Match.
This bit is active only if 32-bit software structures
are used for the descriptor ring entries (SWSTYLE
= ONE, TWO or THREE). Was reserved location,
read and written as ZERO.
New bit: LAFM (bit 21), Logical Address Filter
Match. This bit is active only if 32-bit software
structures are used for the descriptor ring entries
(SWSTYLE = ONE, TWO or THREE). Was re-
served location, read and written as ZERO.
New bit: BAM (bit 20), Broadcast Address Match.
This bit is active only if 32-bit software struc-
tures are used for the descriptor ring entries
(SWSTYLE = ONE, TWO or THREE). Was re-
served location, read and written as ZERO.
New bit: LTINT (bit 28), Last Transmit Interrupt.
This bit is only active, if LTINTEN (CSR5, bit 14) is
set to ONE. This bit location is shared with the
MORE status bit. The host will write the bit as
LTINT and read it as MORE. The P2 will read the
bit as LTINT and write it as MORE.
New bit: BPE (bit 23), Bus Parity Error. This bit is
only active, if 32-bit software structures are used
for the descriptor ring entries (SWSTYLE = ONE,
TWO or THREE) and if APERREN (BCR20, bit 10)
is set to ONE. Was reserved location, read and
written as ZERO.