AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 45

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

The following figure shows a typical burst read access.
The PCnet-PCI II controller arbitrates for the bus, is
granted access, and reads three 32-bit words (DWord)
from the system memory and then releases the bus. In
the example, the memory system extends the data
Basic Non-Burst Write Transfer
By default, the PCnet-PCI II controller uses non-burst
cycles in all bus master write operations. All
PCnet-PCI II controller non-burst write accesses are of
the PCI command type Memory Write (type 7). The
byte enable signals indicate the byte lanes that have
valid data.
The PCnet-PCI II controller typically performs more
than one non-burst write transactions within a single bus
DEVSEL
FRAME
TRDY
IRDY
C/BE
REQ
GNT
PAR
CLK
AD
1
DEVSEL is sampled
Figure 14. Burst Read Transfer (EXTREQ = 0, MEMCMD = 0)
2
ADDR
0110
3
PAR
4
P R E L I M I N A R Y
Am79C970A
5
DATA
phase of the each access by one wait state. The exam-
ple assumes that EXTREQ (BCR18, bit 8) is cleared to
ZERO, therefore, REQ is deasserted in the same cycle
as FRAME is asserted.
mastership period. FRAME is dropped between
consecutive non-burst write cycles. REQ however stays
asserted until FRAME is asserted for the last transac-
tion. The PCnet-PCI II controller supports zero wait
state write cycles except with the case of descriptor
write transfers. (See the section “Descriptor DMA
Transfers” for the only exception.) It asserts IRDY im-
mediately after the address phase and at the same time
starts sampling DEVSEL.
6
0000
PAR
7
DATA
8
PAR
9
DATA
10
PAR
11
19436A-17
AMD
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