AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 161

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

4 bits wide. The values in these fields determine the
number of transmit and receive Descriptor Ring Entries
(DRE) which are used in the descriptor rings. Their
meaning is as follows:
Table 39. R/TLEN Decoding (SSIZE32 = 1)
R/TLEN
11XX
1X1X
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
4
MATCH = 1 Packet Accepted
MATCH = 0 Packet Rejected
Received Message
Destination Address
1
No. of DREs
0
1
128
256
512
512
512
16
32
64
1
2
4
8
Figure 2. Address Match Logic
P R E L I M I N A R Y
CRC
GEN
SEL
Am79C970A
If a value other than those listed in the above table is de-
sired, CSR76 and CSR78 can be written after initializa-
tion is complete.
RDRA and TDRA
TDRA and RDRA indicate where the transmit and re-
ceive descriptor rings begin. Each DRE must be located
at a16-byte address boundary when SSIZE32 is set to
ONE (BCR20, bit 8). Each DRE must be located at an
8-byte address boundary when SSIZE32 is set to ZERO
(BCR20, bit 8).
LADRF
The Logical Address Filter (LADRF) is a 64-bit mask that
is used to accept incoming Logical Addresses. If the first
bit in the incoming address (as transmitted on the wire)
is a ONE, it indicates a logical address. If the first bit is a
ZERO, it is a physical address and is compared against
the physical address that was loaded through the
initialization block.
31
32-Bit Resultant CRC
26
64
6
63
MUX
Address Filter
(LADRF)
Logical
0
0
MATCH
AMD
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