AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 124

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

CSR15: Mode
Bit
31–16 RES
15
14
13
124
AMD
PORTSEL[1:0]
DRCVBC
DRCVPA
PROM
Name
0X
0X
00
01
10
11
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
This register’s fields are loaded
during the PCnet-PCI II controller
initialization routine with the cor-
responding initialization block
values. The host can also write
directly to this register.
Reserved locations. Written as
ZEROs and read as undefined.
Promiscuous Mode.
When PROM is set to ONE,
all incoming receive frames
are accepted.
Read/Write
when either the STOP or the
SPND bit is set.
Disable
When set, this bit disables
the PCnet-PCI II controller from
receiving broadcast messages.
DRCVBC has no effect when
PROM is set to ONE.
Read/Write
when either the STOP or the
SPND bit is set. DRCVBC is
cleared
S_RESET and not affected
by STOP.
Disable Receive Physical Ad-
dress. When set, the physical ad-
dress detection (Station or node
ID) of the PCnet-PCI II controller
will be disabled. Frames ad-
dressed to the node’s individual
physical address will not be rec-
ognized. DRCVPA has no effect
when PROM is set to ONE.
Receive
by
(BCR2[1])
accessible
accessible
accessible
Table 23. Network Port Configuration
ASEL
H_RESET
X
X
1
1
0
0
Broadcast.
P R E L I M I N A R Y
only
only
only
Am79C970A
or
12
11
10
9
(of 10BASE-T)
Link Status
MENDECL
DLNKTST
Pass
DAPC
TSEL
Fail
LRT
LRT
X
X
X
X
Read/Write
when either the STOP or the
SPND bit is set.
Disable
DLNKTST is set to ONE, moni-
toring of Link Pulses is disabled.
When DLNKTST is cleared to
ZERO, monitoring of Link Pulses
is enabled. This bit only has
meaning when the 10BASE-T
network interface is selected.
Read/Write
when either the STOP or the
SPND bit is set.
Disable Automatic Polarity Cor-
rection. When DAPC is set to
ONE, the 10BASE-T receive po-
larity reversal algorithm is dis-
abled. When DAPC is cleared to
ZERO, the polarity reversal algo-
rithm is enabled.
This bit only has meaning when
the 10BASE-T network interface
is selected.
Read/Write
when either the STOP or the
SPND bit is set.
MENDEC Loopback Mode. See
the description of the LOOP bit
in CSR15.
Read/Write
when either the STOP or the
SPND bit is set.
Low Receive Threshold (T-MAU
Mode only)
Transmit Mode Select (AUI
Mode only)
Low Receive Threshold. When
LRT is set to ONE, the internal
twisted pair receive thresholds
are reduced by 4.5 dB below
the standard 10BASE-T value
(approximately 3/5) and the
unsquelch threshold for the
RXD circuit will be 180 mV–
312 mV peak.
Link
Network Port
10BASE-T
10BASE-T
Reserved
accessible
accessible
accessible
accessible
GPSI
AUI
AUI
Status.
When
only
only
only
only