AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 137

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

CSR82: Bus Activity Timer
Bit
31–16 RES
15–0 DMABAT
Name
Description
Reserved locations. Written as
ZEROs and read as undefined.
Bus Activity Timer. If TIMER
(CSR4, bit 13) is set to ONE, this
register controls the maximum
allowable time that PCnet-PCI II
controller will take up on the sys-
tem bus during FIFO data trans-
fers. The Bus Activity Timer does
not limit the time on the system
bus during initialization block or
descriptor transfers.
The DMABAT value is inter-
preted as an unsigned number
with a resolution of 0.1 s. For
instance, a value of 51 s would
be programmed with a value of
510 (1FEh). A value of ZERO
(the default value) will result in a
single data transfer.
DMABAT starts counting down
when the PCnet-PCI II controller
is granted bus ownership and the
bus is idle. When DMABAT has
counted down to ZERO, the
PCnet-PCI II controller will finish
the current data phase before re-
leasing the bus. Note that be-
cause DMABAT does not run on
the PCI bus interface clock, the
actual time the PCnet-PCI II
controller takes up the bus
might differ by 2 to 3 clock
periods from the value pro-
grammed to DMABAT.
DMABAT should not be enabled
when the PCnet-PCI II controller
is used in a PCI bus application.
The PCI Latency Timer should be
the only entity governing the time
the PCnet-PCI II controller has
control over the bus.
Read/Write
when either the STOP or the
SPND bit is set. Note that the
read operation will yield the value
of the run-time copy of the Bus
Activity Timer and not the regis-
ter that holds the programmed
value. Most read operations will
yield a value of ZERO, because
the run-time counter is only
reloaded with the programmed
value at the beginning of a new
bus mastership period. The Bus
Activity Timer register is cleared
accessible
P R E L I M I N A R Y
only
Am79C970A
CSR84: DMA Address Register Lower
Bit
31–16 RES
15–0 DMABAL
CSR85: DMA Address Register Upper
Bit
31–16 RES
15–0 DMABAU
CSR86: Buffer Byte Counter
Bit
31–16 RES
Name
Name
Name
to a value of 0000h after
H_RESET or S_RESET and is
unaffected
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
This register contains the lower
16 bits of the address of system
memory for the current DMA
cycle. The Bus Interface Unit
controls the Address Register
by issuing commands to incre-
ment the memory address for
sequential
DMABAL register is undefined
until the first PCnet-PCI II con-
troller DMA operation.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
This register contains the upper
16 bits of the address of system
memory for the current DMA cy-
cle. The Bus Interface Unit con-
trols the Address Register by
issuing commands to increment
the memory address for sequen-
tial operations. The DMABAU
register is undefined until the
first
DMA operation.
Read/Write
when either the STOP or the
SPND bit is set. These bits are
unaffected
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
PCnet-PCI
by
operations.
accessible
accessible
by
setting
II
H_RESET,
AMD
controller
only
only
137
The
the