AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 129

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

CSR33: Next Transmit Descriptor Address Upper
Bit
31–16 RES
15–0 NXDAU
CSR34: Current Transmit Descriptor Address
Lower
Bit
31–16 RES
15–0 CXDAL
CSR35: Current Transmit Descriptor Address
Upper
Bit
31–16 RES
15–0 CXDAU
CSR36: Next Next Receive Descriptor Address
Lower
Bit
31–16 RES
15–0 NNRDAL
Name
Name
Name
Name
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the upper 16 bits of
the next transmit descriptor
address pointer.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the lower 16 bits of the
current
address pointer.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the upper 16 bits of the
current transmit descriptor ad-
dress pointer.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the lower 16 bits of the
next next receive descriptor
address pointer.
transmit
accessible
accessible
accessible
descriptor
P R E L I M I N A R Y
only
only
only
Am79C970A
CSR37: Next Next Receive Descriptor Address
Upper
Bit
31–16 RES
15–0 NNRDAU
CSR38: Next Next Transmit Descriptor Address
Lower
Bit
31–16 RES
15–0 NNXDAL
CSR39: Next Next Transmit Descriptor Address
Upper
Bit
31–16 RES
15–0 NNXDAU
Name
Name
Name
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the upper 16 bits of the
next next receive descriptor
address pointer.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the lower 16 bits of the
next next transmit descriptor
address pointer.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the upper 16 bits of the
next next transmit descriptor
address pointer.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
accessible
accessible
accessible
accessible
AMD
only
only
only
only
129