AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 58

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

Descriptor DMA Transfers
PCnet-PCI II controller microcode will determine when a
descriptor access is required. A descriptor DMA read
will consist of two data transfers. A descriptor DMA write
will consist of one or two data transfers. The descriptor
DMA transfers within a single bus mastership period will
always be of the same type (either all read or all write).
During descriptor read accesses, the byte enable sig-
nals will indicate that all byte lanes are active. Should
some of the bytes not be needed, then the PCnet-PCI II
controller will internally discard the extraneous informa-
tion that was gathered during such a read.
The settings of SWSTYLE (BCR20, bits 7–0) and
BREADE (BCR18, bit 6) affect the way the PCnet-PCI II
controller performs descriptor read operations.
When SWSTYLE is set to ZERO, ONE or TWO, all
descriptor read operations are performed in non-burst
mode. The setting of BREADE has no effect in
this configuration.
When SWSTYLE is set to THREE, the descriptor entries
are ordered to allow burst transfers. The PCnet-PCI II
controller will perform all descriptor read operations in
burst mode, if BREADE is set to ONE.
58
AMD
P R E L I M I N A R Y
Am79C970A
SWSTYLE
BCR18[6] BCR20[7:0]
1,2
0
3
3
Table 4. Descriptor Read Sequence
BREADE
X
X
0
1
AD Bus Sequence
Address = XXXX XX00h
Turn around cycle
Data = MD1[31:24], MD0[23:0]
Idle
Address = XXXX XX04h
Turn around cycle
Data = MD2[15:0], MD1[15:0]
Address = XXXX XX04h
Turn around cycle
Data = MD1[31:0]
Idle
Address = XXXX XX00h
Turn around cycle
Data = MD0[31:0]
Address = XXXX XX04h
Turn around cycle
Data = MD1[31:0]
Idle
Address = XXXX XX08h
Turn around cycle
Data = MD0[31:0]
Address = XXXX XX04h
Turn around cycle
Data = MD1[31:0]
Data = MD0[31:0]