AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 155

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

14
PREAD
ble BCR locations will be reset to
their H_RESET values. The
contents of the Address PROM
locations,
be cleared.
If the EEPROM detection fails,
then
commands will terminate early
and PVALID will not be set. This
applies to the automatic read of
the EEPROM after H_RESET
as well as to host-initiated
PREAD commands.
Read accessible only. PVALID is
read only. Write operations have
no effect. PVALID is cleared to
ZERO during H_RESET and is
unaffected by S_RESET or by
setting the STOP bit.
EEPROM Read command bit.
When this bit is set to ONE by the
host, the PVALID bit (BCR19, bit
15) will immediately be cleared to
ZERO and then the PCnet-PCI II
controller will perform a read op-
eration of 36 bytes from the
EEPROM through the Microwire
interface. The EEPROM data
that is fetched during the read
will be stored in the appropriate
internal
the
EEPROM contents will be indi-
rectly accessible to the host
through read accesses to the Ad-
dress PROM (offsets 0h through
Fh) and through read accesses
to the EEPROM-programmable
BCRs. Note that read accesses
from these locations will not actu-
ally access the EEPROM itself,
but instead will access the
PCnet-PCI II controller’s internal
copy of the EEPROM contents.
Write accesses to these loca-
tions may change the PCnet-PCI
II controller register contents, but
the EEPROM locations will not
be affected. EEPROM locations
may also be accessed directly
by programming bits 4–0 of
this register.
At the end of the read operation,
the PREAD bit will automatically
be
the PCnet-PCI II controller and
PVALID will be set, provided that
an EEPROM existed on the
Microwire interface pins and that
the checksum for the entire 36
bytes of EEPROM was correct.
PCnet-PCI
cleared
all
registers
attempted
however,
to
II
ZERO
on
controller.
will
P R E L I M I N A R Y
PREAD
board
Am79C970A
not
by
13
EEDET
Note that when PREAD is set to
ONE, the PCnet-PCI II controller
will no longer respond to any ac-
cesses directed toward it, until
the
completed
PCnet-PCI II controller will termi-
nate these accesses with the
assertion of DEVSEL and STOP
while TRDY is not asserted, sig-
naling to the initiator to discon-
nect and retry the access at a
later time.
If a PREAD command is given to
the PCnet-PCI II controller but no
EEPROM is detected at the
Microwire interface pins, the
PREAD command will terminate
early, the PREAD bit will be
cleared to ZERO, the PVALID bit
will remain ZERO, and all
EEPROM-programmable
locations will be reset to their
H_RESET values. The contents
of the Address PROM locations,
however, will not be cleared.
Read accessible always. Write
accessible only when either the
STOP or the SPND bit is set.
PREAD is cleared to ZERO dur-
ing H_RESET and is unaffected
by S_RESET or by setting the
STOP bit.
EEPROM Detect. This bit indi-
cates the sampled value of the
EESK/LED1/SFBD pin at the ris-
ing edge of CLK during the last
clock during which RST is as-
serted. This value indicates
whether or not an EEPROM has
been detected at the EEPROM
interface. If this bit is a ONE, it in-
dicates that an EEPROM has
been detected. If this bit is a
ZERO, it indicates that an
EEPROM has not been detected.
Read accessible always. EEDET
is read only. Write operations
have no effect. It is unaffected by
S_RESET or by setting the
STOP bit.
The following table indicates the
possible combinations of EEDET
and
EEPROM and the resulting op-
erations that are possible on the
EEPROM Microwire interface:
PREAD
the
existence
successfully.
operation
AMD
of
BCR
155
The
has
an