AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 139

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

CSR112: Missed Frame Count
Bit
31–16 RES
15–0
CSR114: Receive Collision Count
Bit
31–16 RES
15–0
Name
Name
MFC
RCC
(CSR0, bit 11) will be set to ONE,
and an interrupt may be gener-
ated, depending upon the setting
of the MERRM bit (CSR3, bit 11)
and the IENA bit (CSR0, bit 6).
The value in this register is inter-
preted as the unsigned number
of XTAL1 clock periods divided
by two, i.e. the value in this regis-
ter is given in 0.1 s increments.
For example, the value 0600h
(1536 decimal) will cause a
MERR to be indicated after
153.6 s of bus latency. A value
of ZERO will allow an infinitely
long bus latency, i.e. bus timeout
error will never occur.
Read/Write
when either the STOP or the
SPND bit is set. This register is
set to 0600h by H_RESET or
S_RESET and is unaffected by
setting the STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Missed Frame Count. Indicates
the number of missed frames.
MFC will roll over to a count of
ZERO from the value 65535. The
MFCO bit (CSR4, bit 8) will be set
each time that this occurs. The
PCnet-PCI II controller will not
count missed frames while the
device is in suspend mode
(SPND = 1, CSR5, bit 0).
Read accessible always. MFC is
read only, write operations are
ignored. MFC is cleared by
H_RESET or S_RESET or by
setting the STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Receive Collision Count. Indi-
cates
collisions
encountered by the receiver
since
the counter.
the
the
on
total
accessible
last
the
number
reset
P R E L I M I N A R Y
network
only
Am79C970A
of
of
CSR122: Advanced Feature Control
Bit
31–16 RES
15–2
0
CSR124: Test Register 1
Bit
RCVALGN
Name
Name
RES
RCC will roll over to a count of
ZERO from the value 65535. The
RCVCCO bit of CSR4 (bit 5) will
be set each time that this occurs.
The PCnet-PCI II controller will
continue counting collisions on
the network while the device is
in suspend mode (SPND = 1,
CSR5, bit 0)
Read accessible always. RCC is
read only, write operations are ig-
nored.
H_RESET or S_RESET or by
setting the STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Reserved locations. Written as
ZEROs and read as undefined.
Receive Frame Align. When set,
this bit forces the data field of
ISO 8802-3 (IEEE/ANSI 802.3)
frames to align to DWord ad-
dress boundaries. It is important
to note that this feature will only
function correctly if all receive
buffer boundaries are DWord
aligned and all receive buffers
have 0 MOD 4 lengths. In order to
accomplish the data alignment,
the PCnet-PCI II controller sim-
ply inserts two bytes of random
data at the beginning of the re-
ceive frame (i.e. before the ISO
8802-3 (IEEE/ANSI 802.3) desti-
nation address field). The MCNT
field reported to the receive de-
scriptor will not include the extra
two bytes.
Read/Write accessible always.
RCVALGN
H_RESET or S_RESET and is
not affected by STOP.
Description
This register is used to place
the PCnet-PCI II controller into
various test modes. Only Runt
Packet Accept and GPSI port en-
able are user accessible test
modes. All other test modes are
for AMD internal use only.
RCC
is
is
cleared
cleared
AMD
139
by
by