ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 18

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

ORCA ORT8850 FPSC
Eight-Channel x 850 Mbits/s Backplane Transceiver
Generic Backplane Transceiver Application
Backplane Transceiver Core Detailed
Description
HSI Macro
The 850 high-speed interface (HSI) provides a physical
medium for high-speed asynchronous serial data trans-
fer between ASIC devices. The devices can be
mounted on the same PC board or mounted on differ-
ent boards and connected through the shelf back-
plane. The 850 CDR macro is an eight-channel clock-
phase select (CPS) and data retime function with
serial-to-parallel demultiplexing for the incoming data
stream and parallel-to-serial multiplexing for outgoing
data. The macrocell can be used as a eight-channel or
16-channel configuration. The ORT8850 uses an eight-
channel HSI macro cell. The HSI macro consists of
three functionally independent blocks: receiver, trans-
mitter, and PLL synthesizer as shown in Figure 4.
The PLL synthesizer block generates the necessary
850 MHz clock for operation from a 212 MHz,
106 MHz, or 85 MHz reference. The PLL synthesizer
block is a common asset shared by all eight receive
and transmit channels. The PLL reference clock must
match the interface frequency.
18
DOUTXX
DINXX
PARALLEL
DATAIN
COMMA _DET
DOUTXX_FP
PARALLEL DATA OUT
SYS_CLK
ERROR FLAG
FIFO
Figure 3. 8850 with 8B/10B Coding/Decoding
ALIGNMENT
TRANSMIT CHANNEL (1 OF 8)
FIFO
8
ENCODER
8B/10B
DECODER
10b/8b
10
RECEIVER CHANNEL (1 OF 8)
The HSI_RX block receives a differential 850 Mbits/s
(or subrates 424 Mbits/s, 212 Mbits/s) serial data with-
out clock at its LVDS receiver input. Based on data
transitions, the receiver selects an appropriate
850 MHz clock phase for each channel to retime the
data. The retimed data and clock are then passed to
the deMUX (deserializer) module. DeMUX module per-
forms serial-to-parallel conversion and provides three
possible parallel rates, 212 Mbits/s, 106 Mbits/s, or
85 Mbits/s, where the 106 Mbits/s data is used in
SONET mode and the 85 Mbits/s data is used in
8B/10B mode (212 Mbits/s is unused).
The HSI_TX block receives 106 Mbits/s (SONET
mode), or 85 Mbits/s (8B/10B mode) parallel data at its
input. MUX (serializer) module performs a parallel-to-
serial conversion using an 850 MHz clock provided by
the PLL/synthesizer block. The resulting 850 Mbits/s
serial data stream is then transmitted through the
LVDS driver.
The loopback feature built into the HSI macro provides
looping of the transmitter data output into the receiver
input when desired.
All rate examples described here are the maximum
rates possible. The actual HSI internal clock rate is
determined by the provided reference clock rate. For
example, if a 78 MHz reference clock is provided, the
HSI macro will operate at 622 Mbits/s.
(continued)
LCKRX
10
CLOCK
DATA
RECOVERY
CLOCK
Agere Systems Inc.
August 2001
Data Sheet
TX LVDS
RX LVDS
1757(F)