ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 22

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

ORCA ORT8850 FPSC
Eight-Channel x 850 Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed Description
Table 2. Transmitter TOH on LVDS Output (Transparent Mode)
In the TOH insert mode of operation, TOH bytes on LVDS output are shown in Table 3. This also shows the order
in which data is transferred to the serial TOH interface, starting with the most significant bit of the first A1 byte. The
first bit of the first byte is replaced by an even parity check bit over all TOH bytes from the previous TOH frame.
Table 3. Transmitter TOH on LVDS Output (TOH Insert Mode)
A1/A2 Frame Insert and Testing
The A1 and A2 bytes provide a special framing pattern that indicates where a STS-1 begins in a bit stream. All
12 A1 bytes of each STS-12 are set to 0xF6, and all 12 A2 bytes of the STS-12 are set to 0x28 when not overrid-
den with an user-specified value for testing. The latency from the transmission of the first bit of the A1 byte at the
device output pins from the transmit frame pulse (SYS_FP) at the FPGA to embedded core input is between five to
seven cycles of fpga_sysclk.
A1/A2 testing (corruption) is controlled per stream by the A1/A2 error insert register. When A1/A2 corruption detec-
tion is set for a particular stream, the A1/A2 values in the corrupted A1/A2 value registers are sent for the number
of frames defined in the corrupted A1/A2 frame count register. When the corrupted A1/A2 frame count register is
set to zero, A1/A2 corruption will continue until the A1/A2 error insert register is cleared. This also allows alternate
values to be set for A1 and A2 during normal operation. For the ORT8850, it is optionally possible to not insert A1
and A2.
On a per-device basis, the A1 and A2 byte values are set, as well as the number of frames of corruption. Then, to
insert the specified A1/A2 values, each channel has an enable register. When the enable register is set, the A1/A2
values are corrupted for the number specified in the number of frames to corrupt. To insert errors again, the per-
channel fault insert register must be cleared, and set again. Only the last A1 and the first A2 are corrupted.
22
A1 A1
B1
A1 A1
B1
D1 D1
H1 H1
D4 D4
D7 D7
D10
S1
Regenerated bytes.
Transparent bytes from parallel input port.
D10
S1
Regenerated bytes.
Inserted or transparent bytes. Blocks of 12 STS-1 bytes are controlled as a whole. There are 15 controls/channel: K1/K2, S1/M0, E1/F1/E2, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
D11, D12.
Transparent bytes (from parallel input port).
Inserted bytes from TOH serial input port.
0
0
A1
A1
D1
H1
D4
D7
D10
S1
0
0
A1 A1
A1 A1
D1 D1
H1 H1
D4 D4
D7 D7
D10
S1
0
0
D10
S1
0
0
A1
A1
D1
H1
D4
D7
D10
S1
0
0
A1 A1
A1 A1
D1 D1
H1 H1
D4 D4
D7 D7
D10
S1
0
0
D10
S1
0
0
A1
A1
D1
H1
D4
D7
D10
S1
0
0
A1 A1
A1 A1
D1 D1
H1 H1
D4 D4
D7 D7
D10
S1
0
0
D10
S1
0
0
A1
A1
D1
H1
D4
D7
D10
S1
0
0
A2 A2
A2 A2
E1
D2 D2
H2 H2
K1 K1
D5 D5
D8 D8
D11
M0
E1
D11
M0
A2
A2
E1
D2
H2
K1
D5
D8
D11
M0
A2 A2
A2 A2
E1
D2 D2
H2 H2
K1 K1
D5 D5
D8 D8
D11
M0
M0
E1
D11
A2
A2
E1
D2
H2
K1
D5
D8
D11
M0
A2 A2
A2 A2
E1
D2 D2
H2 H2
K1 K1
D5 D5
D8 D8
D11
M0
E1
M0
D11
A2
A2
E1
D2
H2
K1
D5
D8
D11
M0
A2 A2
A2 A2
D2 D2
H2 H2
K1 K1
D5 D5
D8 D8
M0
E1
D11
(continued)
E1
M0
D11
A2
A2
E1
D2
H2
K1
D5
D8
D11
M0
D3 D3
H3 H3
K2 K2
D6 D6
D9 D9
F1
D12
E2
F1
D12
E2
D3
H3
K2
D6
D9
F1
D12
E2
D3 D3
H3 H3
K2 K2
D6 D6
D9 D9
D12
E2
F1
F1
D12
E2
D3
H3
K2
D6
D9
F1
D12
E2
Agere Systems Inc.
D3 D3
H3 H3
K2 K2
D6 D6
D9 D9
D12
E2
F1
August 2001
F1
D12
E2
Data Sheet
D3
H3
K2
D6
D9
E2
F1
D12
D3 D3
H3 H3
K2 K2
D6 D6
D9 D9
D12
E2
F1
F1
D12
E2
D3
H3
K2
D6
D9
D12
E2
F1