ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 45

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

Data Sheet
August 2001
Agere Systems Inc.
Memory Map
Table 12. Memory Map Descriptions
fixed rev [0:7]
fixed id lsb [0:7]
fixed id msb [7:0]
scratch pad [0:7]
lockreg msb [0:7]
lockreg lsb [0:7]
global reset com-
mand
Device Register Blocks
lvds lpbk control
ext prot sw en
“rx toh frame” and
“rx toh clk enable”
hiz control
Bit/Register
Name(S)
(continued)
Location
Register
00 [0:7]
01 [0:7]
02 [0:7]
04 [0:7]
05 [0:7]
03 [0:7]
(Hex)
06 [0]
08 [0]
08 [3]
08 [4]
Bit/
Register
Type
preg
sreg
creg
creg
creg
creg
creg
Reset
Value
(Hex)
NA
05
80
80
00
00
00
0
0
0
Eight-Channel x 850 Mbits/s Backplane Transceiver
NA
The scratch pad has no function and is not used anywhere in
the core. However, this register can be written to and read from.
In order to write to registers in memory locations 06~7F, lockreg
msb and lockreg lsb must be respectively set to the values of
05 and 80. If the msb and lsb lockreg values are not set to {05,
80}, then any values written to the registers in memory loca-
tions 06~7F will be ignored.
After reset (both hard and soft), the core is in a write locked
mode. The core needs to be unlocked before it can be written
to.
Also note that the scratch pad register (03) can always be writ-
ten to as it is unaffected by write lock mode.
The global reset command is accessed via the pulse register in
memory address 06. The global reset command is a soft (soft-
ware initiated) reset. Nevertheless, the global reset command
will have the exact reset effect as a hard (RST_N pin) reset.
0
1
ext port
sw en
0
1
TOH_CK_FP_EN = 0, can be used to 3-state RX_TOH_CK_EN and RX_TOH_FP signals.
Function mode.
CDR
0
1
LVDS Protection Switching
- MUX is controlled by software (1 control bit per MUX) reg 09.
- Output buffers’ enables are controlled by software (1 control bit per chan-
nel) reg 20, 38, 50, 68, 80, 98, b0, c8.
MUX is controlled by hardware pins.
lvds_Prot_Switch_[aa,ab,ac,ad,ba,bb,bc,bd]
No loopback.
LVDS loopback, transmit to receive on. Serieal data is looped
back to the rx serial input.
Description
ORCA ORT8850 FPSC
45