ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 58

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

ORCA ORT8850 FPSC
Eight-Channel x 850 Mbits/s Backplane Transceiver
Parallel RapidIO-like Interface Timing Characteristics
Figure 17 illustrates the timing for the receive parallel interfaces A, B, and C (DDR). The recommended operating
conditions for this interface are the same as for the HSI interface show in Table 16. Table 20 shows the worst case
timing parameters for this interface made under these conditions.
Table 20. Parallel Receive Data/Control Timing
Figure 18 illustrates the timing for the transmit parallel interfaces A, B, and C (DDR). The recommended operating
conditions for this interface are the same as for the HSI interface shown in Table 16. Table 21 shows the worst case
timing parameters for this interface under these conditions.
Table 21. Transmit Parallel Data/Control Timing
58
Symbol
Symbol
TXD[7:0]
—
—
t1
t2
t3
RXD[7:0]
TXSOC
TXCLK
—
—
t4
t5
RXSOC
RXCLK
Clock Frequency
Clock Duty Cycle
Clock Rise/Fall Time
Data/Control Setup Time Required
Data/Control Hold Time Required
P
N
N
P
N
N
Clock Frequency
Clock Duty Cycle
Clock rise/Fall Time
Data Delay from Clock Edge
P
P
t5
Parameter
Parameter
t5
Figure 18. Transmit Parallel Data/Control Timing
Figure 17. Receive Parallel Data/Control Timing
t5
t2
Min
510
45
—
—
Min
290
290
40
—
—
t5
t4
–1
t1
t3
–1
Max
266
1.0
55
—
Max
266
1.0
60
—
—
Min
510
45
—
—
Min
270
270
40
—
—
t5
–2
–2
Max
290
1.0
55
—
t5
Max
290
1.0
60
—
—
Min
510
45
—
—
Min
260
260
40
—
—
–3
–3
Max
315
1.0
Agere Systems Inc.
55
—
Max
315
1.0
60
—
—
August 2001
Data Sheet
MHz
Unit
V/ns
MHz
Unit
V/ns
ps
%
5-9085.c(F)
ps
ps
%
2289(F)