ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 23

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

Data Sheet
August 2001
Backplane Transceiver Core Detailed
Description
B1 Calculation and Insertion
In a bit interleaved parity -8 (BIP-8) error check set for
even parity over all the bits of an STS-1 frame B1 is
defined for the first STS-1 in an STS-N only, the B1 cal-
culation block computes a BIP-8 code, using even par-
ity over all bits of the previous STS-12 frame after
scrambling and is inserted in the B1 byte of the current
STS-12 frame before scrambling. Per-bit B1 corruption
is controlled by the force BIP-8 corruption register (reg-
ister address 0F). For any bit set in this register, the
corresponding bit in the calculated BIP-8 is inverted
before insertion into the B1 byte position. Each stream
has an independent fault insert register that enables
the inversion of the B1 bytes. B1 bytes in all other STS-
1s in the stream are filled with zeros. For the ORT8850,
it is optionally possible to not insert B1 and the subse-
quent 11 bytes of zeros.
Stream Disable
When disabled via the appropriate bit in the stream
enable register, the prescrambled data for a stream is
set to all ones, feeding the HSI. The HSI macro is pow-
ered down on a per-stream basis, as are its LVDS out-
puts.
Scrambler
The data stream is scrambled using a frame-synchro-
nous scrambler with a sequence length of 127. The
scrambling function can be disabled by software. The
generating polynomial for the scrambler is 1 + x
This polynomial conforms to the standard SONET
STS-12 data format. The scrambler is reset to 1111111
on the first byte of the SPE (byte following the Z0 byte
in the twelfth STS-1). That byte and all subsequent
bytes to be scrambled are exclusive-ORed, with the
output from the byte-wise scrambler. The scrambler
runs continuously from that byte on throughout the
remainder of the frame. A1, A2, J0, and Z0 bytes are
not scrambled.
System Frame Pulse and Line Frame Pulse
System frame pulse (for transmitter) and line frame
pulse (for receiver) are generated in FPGA logic. A1/A2
framing is used on the link for locating the 8 kHz frame
location. All frames sent to the FPGA are aligned to the
FPGA frame pulse LINE_FP which is provided by the
FPGA to the STM macro. All frames sent from the
Agere Systems Inc.
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Eight-Channel x 850 Mbits/s Backplane Transceiver
+ x
7
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FPGA to the STM will be aligned to the frame pulse
SYS_FP that is supplied to the STM macro. In either
direction, the system frame pulse and line frame pulse
are active for one system clock cycle, indicating the
location of A1 byte of STS#1. They are common to all
eight channels except when the pointer mover and
alignment FIFOs are bypassed. In that case, a line
frame pulse for each receive channel is generated by
the STM macro and passed to the FPGA interface.
Repeater
This block is essentially the inverse of the sampler
block. It receives byte-wide STS-12 rate data from the
TOH insert block. In order to support the quad STS-1
and STS-3 modes of operation, the HSI (622 Mbits/s)
can be connected to a slower speed device (e.g.,
155 Mbits/s or 52 Mbits/s). The purpose of this block is
to rearrange the data being fed to the HSI so that each
bit is transmitted four or twelve times, thus simulating
155 Mbits/s or 51.84 Mbits/s serial data. For example,
in STS-3 mode, the incoming STS-12 stream is com-
posed of four identical STS-3s so only every fourth
byte is used. The bit expansion process takes a single
byte and stretches it to take up 4 bytes each consisting
of
4 copies of the 8 bits from the original byte. In STS-1
mode, every twelfth byte is used and four groups of
3 bytes of the form AAAAAAAA, AAAABBBB, and
BBBBBBBB are forwarded to the HSI. An alternate
method for supplying STS-1 mode is to set the HSI to
run at 207.36 MHz and use the four times repeater
function.
STM Receiver (Backplane
Each of the two STM slices of the ORT8850 has four
receiving channels that can be treated as one STS-48
stream, or treated as independent channels. Incoming
data is received through LVDS serial ports at the data
rate of 622 Mbits/s. The receiver can handle the data
streams with frame offsets of up to ±12 bytes which
would be due to timing skews between cards and along
backplane traces or other transmission medium. In
order for this multichannel alignment capability to oper-
ate properly, it should be noted that while the skew
between channels can be very large, they must oper-
ate at the exact same frequency (0 ppm frequency
deviation), thus requiring that their transmitters be
driven by the same clock source. The received data
streams are processed in the HSI and the STM, and
then passed through the CIC boundary to the FPGA
logic.
ORCA ORT8850 FPSC
FPGA)
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