ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 19

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

Data Sheet
August 2001
Agere Systems Inc.
Backplane Transceiver Core Detailed Description
TSTCLK
CREG BYPASS
CREG LOOPBKEN
LOOPBKCH[(n – 1):0]
DIN[(n – 1):0]
848 Mbits/s
or 424 Mbits/s
or 212 Mbits/s DATA
SYSCLK
106 MHz
or 85 MHz
DOUT[(n –1):0]
848 Mbits/s
or 424 Mbits/s
or 212 Mbits/s DATA
RESETTX
(TEST)
Rx
Tx
Figure 4. HSI Functional Block Diagram
SYNTHESIZER
CLOCK/DATA
ALIGNMENT
(850 MHz)
848 MHz
RETIME
CDR
Eight-Channel x 850 Mbits/s Backplane Transceiver
PLL
1
2
n
(continued)
WORD
ALIGN
TEN
BIT
CONTROL
MODE
1
2
n
ORCA ORT8850 FPSC
COMMADET[(n–1):0]
RXPWRDN[(n – 1):0]
LD[(n – 1):0] TX[9:0]
ENCOMMA[(n–1):0]
LD[(n – 1):0]RX[9:0]
RC[1:0]CK[(n–1):0]
LCKRX[(n – 1):0]
or 85 Mbits/s
or 85 Mbits/s
or 85 Mbits/s
106 Mbits/s
106 Mbits/s
106 Mbits/s
RESETRX
or 85 MHz
106 MHz
EN10BIT
LCKPLL
(TEST)
5-8592(F).b
BLOCK
ASIC
TO
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