ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 35

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

Data Sheet
August 2001
Agere Systems Inc.
RapidIO Interface to Pi-Sched
Octets and Start of Cell
Cells will be transmitted on the high-speed LVDS inputs as octets. The first octet o0 (consisting of
d0_0, d1_0 . . . d7_0) will be present on bits 31:24 on the low-speed 32-bit FPGA bus. Similarly, octet o1 (consist-
ing of d0_1, 1_1 . . . d7_1) will be present on bits 23:16 on the 32-bit bus. Thus, octets will always be transmitted
from first octet to last. The minimum number of octets present on the high-speed ports should always be divisible
by 4, evenly representing the relationship with the 32-bit core of the ASIC interface. The start-of-cell signal is
always aligned with the first octet of each cell. Once the first octet of a cell is received, subsequent octets are part
of an uninterrupted data stream until the entire cell has been received. The number of octets in a cell is determined
by the register bits OCELLSIZE. The RapidIO can support varying minimum cell sizes from four octets up to 124 in
increments of 4. The RapidIO is programmed with the cell size by writing to the OCELLSIZE register via the micro-
processor interface. If the transmitted cell size is less than the programmed cell size, a violation occurs and the
IRXSOCVIOL flag is active. This flag can be ignored if a given minimum cell size is not needed.
RXCLK
RXD[0]
RXD[7]
RXSOC
CAPTURE
INPUT
D
D
266 MHz CLOCK DOMAIN
DATA
CLK
CLK
Figure 14. RapidIO Receive Cell Interface
Q
Q
(continued)
D
D
D
CK
CK
Eight-Channel x 850 Mbits/s Backplane Transceiver
SHIFT REGISTERS
CK
Q
Q
REPEATED 7 TIMES (ONE FOR EACH OF RXD[1:7])
Q
D
D
CK
CK
Q
Q
D Q
133 MHz CLOCK DOMAIN
D Q
D
D
D
D
CK
CK
CK
CK
D Q
Q
Q
Q
Q
ORCA ORT8850 FPSC
D Q
(133 MHz)
WRXCLK
ZRXD_15
ZRXD_15
ZRXD_31
ZRXD_7
ZRXD_23
TO
FPGA
ZRXSOC
0676
35