ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 51

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

Data Sheet
August 2001
Agere Systems Inc.
Memory Map
Table 12. Memory Map Descriptions (continued)
FIFO aligner threshold
error flag
receiver internal path par-
ity error flag
LOF flag
LVDS link B1 parity error
flag
input parallel bus parity
error flag
TOH serial input port par-
ity error flag
FIFO OOS error flag
enable/mask register [0:5]
Bit/Register Name(S)
(continued)
88, a0, b8, d0 [1]
88, a0, b8, d0 [2]
88, a0, b8, d0 [4]
88, a0, b8, d0 [5]
88, a0, b8, d0 [0]
88, a0, b8, d0 [3]
88, a0, b8, d0 [6]
Location (Hex)
28, 40, 58, 70,
28, 40, 58, 70,
28, 40, 58, 70,
28, 40, 58, 70,
28, 40, 58, 70,
28, 40, 58, 70,
28, 40, 58, 70,
29, 41, 59, 71,
89, a1, b9, d1
Bit/Register
[0:5]
Eight-Channel x 850 Mbits/s Backplane Transceiver
Register
Type
iareg
iareg
iareg
iareg
iareg
iareg
iereg
Reset
Value
(Hex)
00
0
0
0
0
0
0
These are the per STS-12 alarm flags.
Loss of frame.
FIFO out of Sysc error flag.
Description
ORCA ORT8850 FPSC
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