ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 76

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

ORCA ORT8850 FPSC
Eight-Channel x 850 Mbits/s Backplane Transceiver
Pin Information
Table 31. Embedded Core/FPGA Interface Signal Description (continued)
76
RapidIO Signals (Channel C) (continued)
RapidIO Signals
wrxclk_c_fpga
utxd_c<31:0>
zrxd_c<31:0>
wutxclk_fpga
zrxsocviol_c
halfclk_fpga
zrxalnviol_c
rstn_utx_c
Pin Name
utxtristn_c
zclkstat_c
utxsoc_c
zrxsoc_c
ytristn_c
(continued)
I/O
O
O
O
O
O
O
O
O
I
I
I
I
I
Transmit data bus containing four octets synchronized with the
rising edge of the 60 MHz—146 MHz WUTXCLK_FPGA
(derived from PLL) is clocked into the transmit FIFO within the
RapidIO.
Start of cell originating with the core and synchronized with the
rising edge of WUTXCLK_FPGA into the transmit FIFO. Indi-
cates that the first data word on TXD_C bus includes the first
octet of a new cell in bit positions <31:24>.
Synchronous reset for all memory elements in the
WUTXCLK_FPGA domain.
Output 3-state enable (active-low). When active, the TXD_C,
TXSOC_C, and TXCLK_C LVDS drivers are 3-stated.
3-state override for transmit outputs (active-low). This signal is
ignored during reset, but takes priority over all 3-state control
signals otherwise.
32-bit data from the receive module. The bus contains four
octets and reflects data received via the high-speed RXD_C
data bus.
Indicates the presence of the first octet of a new cell within the
first 32-bit data word on the RXD_C bus in bit positions
<31:24>.
Indicates a minimum cell violation within the receive module.
This signal will transition active-high coincident with RXSOC.
This indicates that the new cell overran the previous cell and
that the previous cell is in violation of the minimum cell size.
Indicates an alignment error. An active state signals RXSOC
was captured on a negative RXCLK edge. This signal will stay
high for a single WRXCLK_C_FPGA cycle coincident with
RXSOC.
Indicates the loss or absence of a clock on the LVDS clock
(RXCLK). After the validation of the absence of the clock, this
signal will stay high for the duration of the absence of the
clock.
Derived from high-speed LVDS clock RXCLK (= RXCLK/2).
One X core clock (60 MHz—146 MHz) generated from an
internal PLL circuit. Input data on UTXD<31:0> and UTXSCO
are synchronous to this clock. The transmit FIFO inputs are
clocked by this clock. The test interface module also runs off
this clock. This clock is sent to the FPGA logic.
1/2 X main PLL output clock. Phase aligned with PFCLK.
Nominal frequency range is 30 MHz to 73 MHz. Duty cycle
spec is 47%/53%.
Description
Agere Systems Inc.
August 2001
Data Sheet