ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 47

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

Data Sheet
August 2001
Agere Systems Inc.
Memory Map
Table 12. Memory Map Descriptions (continued)
input/output parallel bus
parity control
scrambler/descrambler
control
transmit B1 error insert
mask [0:7]
ch 1 int
ch 2 int
ch 3 int
ch 4 int
per device int
enable/mask register for
ch 1-4 + device[4:0]
ch 5 int
ch 6 int
ch 7 int
ch 8 int
enable/mask register for
ch 5-8 [0:3]
frame offset error flag
write to locked register
error flag
enable/mask register [0:1]
STM A mode control
STM B mode control
individual alignment
resync register
group alignment resync
register
Bit/Register Name(S)
(continued)
Location
Register
0F [0:7]
11 [0:4]
15 [0:3]
13 [0:1]
16 [2:3]
16 [0:1]
17 [0:7]
18 [0:7]
0C [5]
0C [6]
(Hex)
10 [0]
10 [1]
10 [2]
10 [3]
10 [4]
14 [0]
14 [1]
14 [2]
14 [3]
12 [0]
12 [1]
Bit/
Register
Type
isreg
isreg
isreg
isreg
isreg
iereg
isreg
isreg
isreg
isreg
iereg
iareg
iareg
iereg
creg
creg
creg
creg
creg
creg
creg
Eight-Channel x 850 Mbits/s Backplane Transceiver
Reset
Value
(Hex)
00
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Consolidation interrupts. 1 = interrupt, 0 = no interrupt.
If in the receive direction the phase offset between any two
channels exceeds 17 bytes, then a frame offset error event
will be issued. This condition is continuously monitored.
If the core memory map has not been unlocked (by writing
to the lock registers), and any address other than the lock-
reg registers or scratch pad register is written to, then a
“write to locked register” event will be generated.
Write 1 to resync stream.
Write 1 to resync selected grouping.
00 - Quad STS-12 or STS-48.
01 - Quad STS-3.
10 - Quad STS-1.
00 - Quad STS-12 or STS-48.
01 - Quad STS-3.
10 - Quad STS-1.
0
1
0
1
0
1
Even parity.
Odd parity.
no rx direction, descramble / tx direction scramble.
In rx direction, descramble channel after SONET frame recov-
ery.
In tx direction, scramble data just before parallel-to-serial con-
version.
No error insertion.
Invert corresponding bit in B1 byte.
Description
ORCA ORT8850 FPSC
47