ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 24

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

ORCA ORT8850 FPSC
Eight-Channel x 850 Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed
Description
Framer Block
The framer block takes byte-wide data from the HSI,
and outputs a byte-aligned, byte-wide data stream and
8 kHz sync pulse. The framer algorithm determines the
out-of-frame/in-frame status of the incoming data and
will cause interrupts on both an errored frame and an
out-of-frame (OOF) state. The framer detects the A1/
A2 framing pattern and generates the 8 kHz frame
pulse. When the framer detects OOF, it will generate
an interrupt. Also, the framer detects an errored frame
and increments an A1/A2 frame error counter. The
counter can be monitored by a processor to compile
performance status on the quality of the backplane.
Because the ORT8850 is intended for use between it
and another ORT8850 or other devices via a back-
plane, there is only one errored frame state. Thus, after
two transitions are missed, the state machine goes into
the OOF state and there is no severely errored frame
(SEF) or loss-of-frame (LOF) indication.
B1 Calculate
Each Rx block receives byte-wide scrambled
77.76 MHz data and a frame sync from the framer.
Since each HSI is independently clocked, the Rx block
operates on individual streams. Timing signals required
to locate overhead bytes to be extracted are generated
internally based on the frame sync. The Rx block pro-
duces byte-wide (optionally) descrambled data and an
output frame sync for the alignment FIFO block. The
frame sync signals are also sent to the FPGA logic for
use when the alignment FIFO block is bypassed.
The B1 calculation block computes a BIP-8 (bit inter-
leaved parity 8 bits) code, using even parity over all bits
of the previous STS-12 frame before descrambling;
this value is checked against the B1 byte of the current
frame after descrambling. A per-stream B1 error
counter is incremented for each bit that is in error. The
error counter may be read via the CPU interface.
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(continued)
Descrambling. The streams are descrambled using a
frame synchronous descrambler with a sequence
length of 127 with a generating polynomial of 1 + x
x
(J0) and the growth bytes (Z0) are not descrambled.
The descrambling function can be disabled by soft-
ware.
Sampler. This block operates on the byte-wide data
directly from the HSI macro. The HSI external interface
always runs at 622 Mbits/s (STS-12), or 850 Mbits/s,
but it can be connected directly to a 155 Mbits/s STS-3
stream or a 51.84 Mbits/s STS-1 stream. If connected
to either a 155 Mbits/s or 51.84 Mbits/s stream, each
incoming data is received either 4 or 12 times respec-
tively. This block is used to return the byte stream to
the expected STS-12 format. The mode of operation is
controlled by a register and can either be STS-12
(pass-through), STS-3 (every fourth bit), or STS-1
(every twelfth bit). The output from this block is not bit-
aligned (i.e., an 8-bit sample does not necessarily con-
tain an entire SONET byte), but it is in standard
SONET STS-12 format (i.e., four STS-3s or 12 STS-
1s) and is suitable for framing.
AIS-L Insertion. Alarm indication signal (AIS) is a con-
tinuous stream of unframed 1s sent to alert down-
stream equipment that the near-end terminal has
failed, lost its signal source, or has been temporarily
taken out of service. If enabled in the AIS_L force reg-
ister, AIS-L is inserted into the received frame by writ-
ing all ones for all bytes of the descrambled stream.
AIS-L Insertion on Out-of-Frame. If enabled via a
register, AIS-L is inserted into the received frame by
writing all ones for all bytes of the descrambled stream
when the framer indicates that an out-of-frame condi-
tion exists.
Internal Parity Generation
Even parity is generated on all data bytes and is routed
in parallel with the data to be checked before the pro-
tection switch MUX at the parallel output.
7
. The A1/A2 framing bytes, the section trace byte
Agere Systems Inc.
August 2001
Data Sheet
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