ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 9

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

Data Sheet
August 2001
Description
The SLIC is connected from PLC routing resources
and from the outputs of the PFU. It contains eight 3-
state, bidirectional buffers, and logic to perform up to a
10-bit AND function for decoding, or an AND-OR with
optional INVERT to perform PAL-like functions. The 3-
state drivers in the SLIC and their direct connections
from the PFU outputs make fast, true, 3-state buses
possible within the FPGA, reducing required routing
and allowing for real-world system performance.
Programmable I/O
The Series 4 PIO addresses the demand for the flexi-
bility to select I/Os that meet system interface require-
ments. I/Os can be programmed in the same manner
as in previous ORCA devices, with the additional new
features which allow the user the flexibility to select
new I/O types that support high-speed interfaces.
Each PIO contains four programmable I/O pads and is
interfaced through a common interface block to the
FPGA array. The PIO is split into two pairs of I/O pads
with each pair having independent clock enables, local
set/reset, and global set/reset. On the input side, each
PIO contains a programmable latch/flip-flop which
enables very fast latching of data from any pad. The
combination provides for very low setup requirements
and zero hold times for signals coming on-chip. It may
also be used to demultiplex an input signal, such as a
multiplexed address/data signal, and register the sig-
nals without explicitly building a demultiplexer with a
PFU.
On the output side of each PIO, an output from the
PLC array can be routed to each output flip-flop, and
logic can be associated with each I/O pad. The output
logic associated with each pad allows for multiplexing
of output signals and other functions of two output sig-
nals.
The output FF, in combination with output signal multi-
plexing, is particularly useful for registering address
signals to be multiplexed with data, allowing a full clock
cycle for the data to propagate to the output. The out-
put buffer signal can be inverted, and the 3-state con-
trol can be made active-high, active-low, or always
enabled. In addition, this 3-state signal can be regis-
Agere Systems Inc.
(continued)
Eight-Channel x 850 Mbits/s Backplane Transceiver
tered or nonregistered.
The Series 4 I/O logic has been enhanced to include
modes for speed uplink and downlink capabilities.
These modes are supported through shift register
logic, which divides down incoming data rates or multi-
plies up outgoing data rates. This new logic block also
supports high-speed DDR mode requirements where
data is clocked into and out of the I/O buffers on both
edges of the clock.
The new programmable I/O cell allows designers to
select I/Os which meet many new communication stan-
dards permitting the device to hook up directly without
any external interface translation. They support tradi-
tional FPGA standards as well as high-speed, single-
ended, and differential-pair signaling (as shown in
Table 1). Based on a programmable, bank-oriented I/O
ring architecture, designs can be implemented using
3.3 V, 2.5 V, 1.8 V, and 1.5 V referenced output levels.
Routing
The abundant routing resources of the Series 4 archi-
tecture are organized to route signals individually or as
buses with related control signals. Both local and glo-
bal signals utilize high-speed buffered and nonbuffered
routes. One PLC segmented (x1), six PLC segmented
(x6), and bused half-chip (xHL) routes are patterned
together to provide high connectivity with fast software
routing times and high-speed system performance.
Eight fully distributed primary clocks are routed on a
low-skew, high-speed distribution network and may be
sourced from dedicated I/O pads, PLLs, or the PLC
logic. Secondary and edge-clock routing is available for
fast regional clock or control signal routing for both
internal regions and on device edges. Secondary clock
routing can be sourced from any I/O pin, PLLs, or the
PLC logic.
The improved routing resources offer great flexibility in
moving signals to and from the logic core. This flexibil-
ity translates into an improved capability to route
designs at the required speeds when the I/O signals
have been locked to specific pins.
ORCA ORT8850 FPSC
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