ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 40

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ORT8850H

Manufacturer Part Number
ORT8850H
Description
Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
Manufacturer
AGERE [Agere Systems]
Datasheet

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ORCA ORT8850 FPSC
Eight-Channel x 850 Mbits/s Backplane Transceiver
Memory Map
This table is constructed to show the correct values when read and written via the system bus MPI interface. When
using this table while interfacing with the system bus user logic master interface, the data values will need to be
byte flipped. This is due to the opposite orientation of the MPI and master interface bus ordering. More information
on this can be found in the MPI/System Bus Application Note (AP01-032NCIP).
Table 11. Memory Map (This table resides at memory offset 0X30000 in the ORT8850.)
40
Device Register Block
ADDR
[7:0]
00
01
02
03
04
05
06
08
09
0a
0b
0d
0e
0c
0f
Register
Type
preg
sreg
sreg
sreg
creg
creg
creg
creg
creg
creg
creg
creg
creg
creg
creg
(continued)
select for
parallel
output
MUX
ch#7
DB7
port
select for
parallel
descra-
scram-
control
output
mbler
MUX
ch#5
DB6
bler/
port
select for
parallel
control
output
output
serial
input/
parity
MUX
ch#7
DB5
port
bus
transmitter B1 error insert mask [0:7]
a1 error insert value [0:7]
a2 error insert value [0:7]
serial port
select for
line lpbk
enable”
and “rx
control
control
“rx toh
frame”
toh clk
fixed id msb [0:7]
lockreg msb [0:7]
output
scratch pad [0:7]
lockreg lsb [0:7]
MUX
ch#5
DB4
fixed id lsb [0:7]
hiz
fixed rev [0:7]
FIFO aligner threshold value (max) [0:4]
FIFO aligner threshold value (min) [0:4]
select for
ext prot
parallel
output
sw en
number of consecutive A1 A2 errors to
MUX
ch#3
DB3
port
select for
parallel
output
MUX
ch#1
DB2
port
generate [0:3]
select for
output
serial
MUX
ch#3
DB1
port
select for
comman
lvds lpbk
control
global
output
(CDR
serial
MSB
reset
only)
MUX
ch#1
DB0
port
d
Agere Systems Inc.
FF (4 ch
was 0F)
Reset
Value
[7:0]
NA
A8
05
80
80
00
00
00
00
40
06
00
00
00
August 2001
Data Sheet
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