ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 63

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

Data Sheet
August 2001
Agere Systems Inc.
Pin Information
This section describes the pins and signals that perform FPGA-related functions. During configuration, the user-
programmable I/Os are 3-stated and pulled up with an internal resistor. If any FPGA function pin is not used (or not
bonded to package pin), it is also 3-stated and pulled up after configuration.
Table 29
* The FPGA States of Operation section contains more information on how to control these signals during start up. The timing of DONE release
Dedicated Pins
CFG_IRQ/MPI_IRQ
is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all
user I/Os) is controlled by a second set of options.
RD_DATA/TDO
Symbol
RD_CFG
PTEMP
V
V
RESET
DONE
V
CCLK
PRGM
GND
DD
DD
DDIO
.
FPGA Common-Function Pin Description
33
15
I/O
— 3 V positive power supply.
— 1.5 V positive power supply for internal logic.
— Positive power supply used by I/O banks.
— Ground supply.
O RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides configu-
O
O As an active-high, open-drain output, a high level on this signal indicates that configura-
O During JTAG, slave, master, and asynchronous peripheral configuration assertion on this
I
I
I
I
I
I
As an input, a low level on DONE delays FPGA start up after configuration.*
Temperature sensing diode pin. Dedicated input.
During configuration,
After configuration,
which causes all PLC latches/FFs to be asynchronously set/reset.
In the master and asynchronous peripheral modes, CCLK is an output which strobes con-
figuration data in. In the slave or readback after configuration, CCLK is input synchronous
with the data on DIN or D[7:0]. CCLK is an output for daisy-chain operation when the lead
device is in master, peripheral, or system bus modes.
tion is complete. DONE has an optional pull-up resistor.
PRGM
ary scan circuitry. This pin always has an active pull-up.
This pin must be held high during device initialization until the
always has an active pull-up.
During configuration,
and 3-states all of the I/O.
After configuration,
TS_ALL function as described above, or, if readback is enabled via a bit stream option, a
high-to-low transition on
PFU output states, starting with frame address 0.
ration data out. If used in boundary scan, TDO is test data out.
CFG_IRQ
MPI active-low interrupt request output.
is an active-low input that forces the restart of configuration and resets the bound-
(active-low) indicates an error or errors for block RAM or FPSC initialization.
RESET
RD_CFG
RESET
RD_CFG
Eight-Channel x 850 Mbits/s Backplane Transceiver
RD_CFG
can be used as a general FPGA input or as a direct input,
can be selected (via a bit stream option) to activate the
forces the restart of configuration and a pull-up is enabled.
is an active-low input that activates the TS_ALL function
will initiate readback of the configuration data, including
Description
ORCA ORT8850 FPSC
INIT
pin goes high. This pin
63