ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 56

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

ORCA ORT8850 FPSC
Eight-Channel x 850 Mbits/s Backplane Transceiver
Power Supply Decoupling LC Circuit
The 850 MHz HSI macro contains both analog and digital circuitry. The data recovery function, for example, is
implemented as primarily a digital function, but it relies on a conventional analog phase-locked loop to provide its
850 MHz reference frequency. The internal analog phase-locked loop contains a voltage-controlled oscillator. This
circuit will be sensitive to digital noise generated from the rapid switching transients associated with internal logic
gates and parasitic inductive elements. Generated noise that contains frequency components beyond the band-
width of the internal phase-locked loop (about 3 MHz) will not be attenuated by the phase-locked loop and will
impact bit error rate directly. Thus, separate power supply pins are provided for these critical analog circuit ele-
ments.
Additional power supply filtering in the form of a LC pi filter section will be used between the power supply source
and these device pins as shown in Figure 16. The corner frequency of the LC filter is chosen based on the power
supply switching frequency, which is between 100 kHz and 300 kHz in most applications.
Capacitors C1 and C2 are large electrolytic capacitors to provide the basic cut-off frequency of the LC filter. For
example, the cutoff frequency of the combination of these elements might fall between 5 kHz and 50 kHz. Capaci-
tor C3 is a smaller ceramic capacitor designed to provide a low-impedance path for a wide range of high-frequency
signals at the analog power supply pins of the device. The physical location of capacitor C3 must be as close to the
device lead as possible. Multiple instances of capacitors C3 can be used if necessary. The recommended filter for
the HSI macro is shown below: L = 4.7 H, RL = 1 , C1 = 0.01 F, C2 = 0.01 F, C3 = 4.7 F.
The Rapid IO interface to Pi-Sched also has internal PLLs that require an analog supply, V
power supply filter network shown above should be repeated and applied to the V
is used. If both the Rapid IO interface and the HSI interface are used, two seperate copies of this interface should
be used.
If the programmable PLLs on the FPGA potrion of the device are to be used, then the V
in the same way. More information on this and other requirements for the FPGA PLLs can be found in the Series 4
PLL application note.
56
Figure 16. Sample Power Supply Filter Network for Analog HSI Power Supply Pins
FROM POWER
SUPPLY SOURCE
+
C1
L
+
C2
+
C3
TO DEVICE
V
PLL_V
DDA
_STM
DD
SSA
A_SHIM inputs if this interface
DD
33 supply must isolated
DD
A_SHIM. The same
Agere Systems Inc.
August 2001
Data Sheet
5-9344(F)