ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 69

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

Data Sheet
August 2001
Agere Systems Inc.
Pin Information
Table 30. FPSC Function Pin Description (continued)
RapidIO LVDS Interface Pins (Transmitter)
MISC System Signals
txd_a_p<7:0>
txd_a_n<7:0>
txd_b_p<7:0>
txd_b_n<7:0>
txd_c_p<7:0>
txd_c_n<7:0>
txsoc_a_p
txsoc_a_n
txsoc_b_p
txsoc_b_n
txsoc_c_p
txsoc_c_n
sys_clk_p
sys_clk_n
txclk_a_p
txclk_a_n
txclk_b_p
txclk_b_n
txclk_c_p
txclk_c_n
lvctap_sk
lvctap_gk
Symbol
gclk_p
gclk_n
rst_n
dxp
dxn
(continued)
I/O
—
—
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
LVDS data for RapidIO, transmitter port A.
LVDS data for RapidIO, transmitter port A.
LVDS start-of-cell for RapidIO, transmitter port A.
LVDS start-of-cell for RapidIO, transmitter port A.
LVDS receive clock for RapidIO, transmitter port A.
LVDS receive clock for RapidIO, transmitter port A.
LVDS data for RapidIO, transmitter port B.
LVDS data for RapidIO, transmitter port B.
LVDS start-of-cell for RapidIO, transmitter port B.
LVDS start-of-cell for RapidIO, transmitter port B.
LVDS receive clock for RapidIO, transmitter port B.
LVDS receive clock for RapidIO, transmitter port B.
LVDS data for RapidIO, transmitter port C.
LVDS data for RapidIO, transmitter port C.
LVDS start-of-cell for RapidIO, transmitter port C.
LVDS start-of-cell for RapidIO, transmitter port C.
LVDS receive clock for RapidIO, transmitter port C.
LVDS receive clock for RapidIO, transmitter port C.
Reset the core only. The FPGA logic is not reset by rst_n.
Internal pull down allows chip to stay in reset state when external driver
loses power.
LVDS system clock, 50% duty cycle, also the reference clock of PLL.
LVDS system clock, 50% duty cycle, also the reference clock of PLL.
LVDS clock for RapidIO PLL internal pull-up.
LVDS clock for RapidIO PLL internal pull-up.
Temperature-sensing diode (anode +).
Temperature-sensing diode (cathode –).
LVDS center-tap for sys_clk (use 0.01 µf to GND).
LVDS center-tap for gclk (use 0.01 µf to GND).
Eight-Channel x 850 Mbits/s Backplane Transceiver
Description
ORCA ORT8850 FPSC
69