ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 27

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

Data Sheet
August 2001
Agere Systems Inc.
Backplane Transceiver Core Detailed Description
Note:
SPE signal behavior shown in this figure is just for illustration purposes: SPE behavior is dependent on pointer movements and concatenation.
SPE signal must be high during negative stuff opportunity byte time slots (H3) for which valid data is carried (negative stuffing).
SPE signal must be low during positive stuff opportunity byte time slots for which there is no valid data (positive stuffing).
STM FIFO Alignment (Backplane
The alignment FIFO allows the transfer of all data to the system clock. The FIFO sync block (Figure 8) allows the
system to be configured to allow the frame alignment of multiple slightly varying data streams. This optional align-
ment ensures that matching STS-12 streams will arrive at the FPGA end in perfect data sync. The frame alignment
is configurable to allow for the possibility of fully independent (i.e., total frame misalignment) STS-12s.
STS-12
STS-12
SPE
H1 H1 H1 H1 H1 H1 H1 H1 H1 H1 H1 H1 H2 H2 H2 H2 H2 H2 H2 H2 H2 H2 H2 H2 H3 H3 H3 H3 H3 H3 H3 H3 H3 H3 H3 H3
SPE SIGNAL SHOWS NEGATIVE STUFFING FOR 2ND STS-1,
AND POSITIVE STUFFING FOR 6TH STS-1
FPGA)
TOH ROW # 4
Figure 7. SPE Stuff Bytes
Eight-Channel x 850 Mbits/s Backplane Transceiver
OPPORTUNITY BYTES
NEGATIVE STUFF
(continued)
1 2 3 4 5 6 7 8 9 10 11 12
OPPORTUNITY BYTES
ORCA ORT8850 FPSC
POSITIVE STUFF
SPE ROW # 4
5-9331
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