ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 71

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

Data Sheet
August 2001
Agere Systems Inc.
Pin Information
Table 31. Embedded Core/FPGA Interface Signal Description (continued)
STM or 8B/10B Signals (continued)
doutad<7:0>
doutba<7:0>
doutbb<7:0>
doutbd<7:0>
doutac<7:0>
doutbc<7:0>
doutac_c1j1
doutad_c1j1
doutba_c1j1
doutbb_c1j1
doutbc_c1j1
doutbd_c1j1
doutac_spe
doutad_spe
doutba_spe
doutbb_spe
doutbc_spe
doutbd_spe
doutad_par
doutba_par
doutbb_par
doutbd_par
doutac_par
doutbc_par
doutac_en
doutad_en
doutba_en
doutbb_en
doutbc_en
doutbd_en
Pin Name
doutad_fp
doutba_fp
doutbb_fp
doutbd_fp
doutac_fp
doutbc_fp
(continued)
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Parallel bus of STM slice A, receiver C. MSB is bit 7.
Parity for parallel bus of STM slice A, receiver C.
SPE signal for parallel bus of STM slice A, receiver C.
C1J1 signal for parallel bus of STM slice A, receiver C.
Enable for parallel bus of STM slice A, receiver C.
Frame pulse or COMMADET for parallel bus of STM slice A, receiver C.
Parallel bus of STM slice A, receiver D. MSB is bit 7.
Parity for parallel bus of STM slice A, receiver D.
SPE signal for parallel bus of STM slice A, receiver D.
C1J1 signal for parallel bus of STM slice A, receiver D.
Enable for parallel bus of STM slice A, receiver D.
Frame pulse or COMMADET for parallel bus of STM slice A, receiver D.
Parallel bus of STM slice B, receiver A. MSB is bit 7.
Parity for parallel bus of STM slice B, receiver A.
SPE signal for parallel bus of STM slice B, receiver A.
C1J1 signal for parallel bus of STM slice B, receiver A.
Enable for parallel bus of STM slice B, receiver A.
Frame pulse or COMMADET for parallel bus of STM slice B, receiver A.
Parallel bus of STM slice B, receiver B. MSB is bit 7.
Parity for parallel bus of STM slice B, receiver B.
SPE signal for parallel bus of STM slice B, receiver B.
C1J1 signal for parallel bus of STM slice B, receiver B.
Enable for parallel bus of STM slice B, receiver B.
Frame pulse or COMMADET for parallel bus of STM slice B, receiver B.
Parallel bus of STM slice B, receiver C. MSB is bit 7.
Parity for parallel bus of STM slice B, receiver C.
SPE signal for parallel bus of STM slice B, receiver C.
C1J1 signal for parallel bus of STM slice B, receiver C.
Enable for parallel bus of STM slice B, receiver C.
Frame pulse or COMMADET for parallel bus of STM slice B, receiver C.
Parallel bus of STM slice B, receiver D. MSB is bit 7.
Parity for parallel bus of STM slice B, receiver D.
SPE signal for parallel bus of STM slice B, receiver D.
C1J1 signal for parallel bus of STM slice B, receiver D.
Enable for parallel bus of STM slice B, receiver D.
Frame pulse or COMMADET for parallel bus of STM slice B, receiver D.
Eight-Channel x 850 Mbits/s Backplane Transceiver
Description
ORCA ORT8850 FPSC
71