ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 30

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

ORCA ORT8850 FPSC
Eight-Channel x 850 Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed Description
8B/10B Transmitter (FPGA
For each channel, an 8B/10B encoder can be enabled in place of the STM transmitter. This block receives 8-bit
data from the FPGA interface, encodes it into a 10-bit code, and then sends this 10-bit code to the HSI block for
serialization and transmission from the ORT8850. This 8-bit to 10-bit encoding provides for guaranteed transmis-
sion of a large number of transmissions to allow for easy recovery by a CDR on the other end of the backplane or
transmission medium, and also allows for the insertion of control characters. These control characters have many
uses, including their use in the ORT8850 to align 10-bit word boundries and perform multi-channel alignments, as
will be discussed in the 8B/10B receiver section.
The data input to the transmitter of each channel from the FPGA logic is an 8-bit word and K-control input. The K-
control input is used to designate data or a special character, where a logic 1 indicates that the data should be
mapped to a control character. The following table shows this mapping that is supported. Two different codings are
possible for each data value and are shown as encoded word (+) and encoded word (–). The transmitter selects
between the positive or negative encoded word based on the calculated disparity of the present data.
Table 6. Valid Special Characters
It should also be noted that the data is serialized in the reverse order from the STM block, where dinxy[0] is trans-
mitted first (the 8B/10B receive block also deserializes in the reverse order of the STM receive block).
8B/10B Receiver (Backplane
Instead of using the STM receiver block in the ORT8850, a separate decoder block is available to allow for receiv-
ing data that has been encoded using a standard 8B/10B encoder. This encoding/decoding scheme also allows for
the transmission of special characters and allows for error detection.
Clock recover for the 8B/10B decoder is performed by the HSI block for each of the eight receive channels in the
ORT8850. This recovered data is then aligned to a 10-bit word boundry by detecting and aligning to the comma-
codeword. Word alignment is done to either polarity of this codeword. The 10-bit code word is passed to the
decoder, which provides an 8-bit byte of data and a COMMADET signal to the multi-channel alignment block. In
8B/10B mode, the receiver can handle ± 12 bytes of skew between channels which would be due to timing skews
between cards and along backplane trace or other transmission medium. In order for this multi-channel alignment
capability to operate properly, it should be noted that while the skew between channels can be very large, they
must operate at the exact same frequency (0 ppm frequency deviation), thus requiring their transmitters to be
driven by the same clock source. This alignment FIFO can be bypassed. The COMMADET signal is also provided
to the FPGA logic per channel on the signal doutxy_fp, where x designates either four-channel macro A or B, while
y designates the channel (A, B, C, D) in each macro.
30
K character
K28.0
K28.1
K28.2
K28.3
K28.4
K28.5
K28.6
K28.7
K23.7
K27.7
K29.7
K30.7
HGF EDCBA
765 43210
000 11100
001 11100
010 11100
100 11100
101 11100
011 11100
110 11100
111 11100
111 10111
111 11011
111 11101
111 11110
Backplane)
FPGA)
K control
1
1
1
1
1
1
1
1
1
1
1
1
(continued)
Encoded Word (–)
001111 0100
001111 1001
001111 0101
001111 0010
001111 1010
001111 1000
111010 1000
110110 1000
101110 1000
011110 1000
001111 0011
001111 0110
abcdei fghj
Encoded Word (+)
Agere Systems Inc.
110000 1011
110000 0110
110000 1010
110000 1100
110000 1101
110000 0101
110000 1001
000101 0111
001001 0111
010001 0111
100001 0111
110000 0111
abcdei fghj
August 2001
Data Sheet